PTAB

IPR2025-01487

Infineon Technologies Americas Corp v. Conversant Intellectual Property Management Corp

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: MEMORY WITH OUTPUT CONTROL
  • Brief Description: The ’381 patent discloses a memory architecture intended to improve the speed and capacity of semiconductor flash memory devices. The technology utilizes serial data interfaces to create low-pin-count devices that can be cascaded in a daisy-chain configuration.

3. Grounds for Unpatentability

Ground 1: Claims 1-21 are obvious over Grundy in view of Kilbuck.

  • Prior Art Relied Upon: Grundy (Application # 2004/0148482) and Kilbuck (Application # 2005/0204091).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Grundy and Kilbuck discloses all limitations of the challenged claims. Grundy was asserted to teach the core architecture of a high-speed memory system, including a plurality of memory devices coupled in a chain. Specifically, Grundy allegedly disclosed a flash memory device (describing "flash EEPROM"), a clock input port, a common data interface using multi-purpose lines to transfer command and data values, and a double data rate (DDR) configuration where data is transferred on both rising and falling clock edges. Grundy was also argued to teach a control input port for receiving a control signal that indicates the beginning and end of command data transfer, control circuitry for executing read/write operations, and the use of status requests. To the extent Grundy did not explicitly detail certain conventional flash memory features, Petitioner contended that Kilbuck supplied these teachings. Kilbuck was cited for its disclosure of standard flash memory attributes, such as the organization of memory into erasable blocks and pages, the use of NAND/NOR architectures, single-level and multi-level cells, and the inclusion of an internal status register to monitor memory status. Petitioner argued that implementing Grundy's chained memory system with the conventional flash memory features described in Kilbuck would have rendered the claimed invention obvious. For example, while Grundy taught status requests, Kilbuck explicitly taught an internal status register, which a person of ordinary skill in the art (POSITA) would have naturally used to fulfill Grundy’s function.
    • Motivation to Combine: Petitioner asserted several motivations for a POSITA to combine the teachings of Grundy and Kilbuck. First, Grundy disclosed using flash memory in its system but left the specific implementation details to the discretion of a POSITA. Kilbuck, being in the same field, provided these exact conventional details for flash memory systems, making it a natural reference to consult. Second, Kilbuck disclosed supportive circuitry, such as error correction codes (ECC) and internal program verification, which a POSITA would have been motivated to incorporate into Grundy’s system to improve its reliability and performance. Third, the combination represented the simple application of a known technique (Kilbuck’s flash memory implementation) to a known system (Grundy’s memory chain architecture) to achieve the predictable result of a functional and reliable high-speed flash memory system.
    • Expectation of Success: Petitioner argued that a POSITA would have had a reasonable expectation of success in combining the references. Both Grundy and Kilbuck describe systems and techniques related to non-volatile flash memory. Combining these known elements, each performing its well-understood function, would have predictably resulted in a working memory system with the claimed features.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-21 of the ’381 patent as unpatentable.