PTAB

IPR2025-01489

Infineon Technologies Americas Corp v. HP Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Distributed Multiplexing Circuit with Built-In Repeater
  • Brief Description: The ’448 patent discloses systems for distributing multiplexer functionality to address routing congestion and design difficulties on integrated circuits. The invention describes a distributed multiplexor logic (DML) circuit comprising a plurality of stages that select between multiple data connections to choose and transmit a selected data word.

3. Grounds for Unpatentability

Ground 1: Obviousness over Pixley and Watanabe - Claims 1-21 are obvious over Pixley in view of Watanabe.

  • Prior Art Relied Upon: Pixley (Patent 5,572,535) and Watanabe (Application # 2003/0056080).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that the combination of Pixley and Watanabe taught every limitation of the challenged claims. Pixley disclosed a "typical" nested multiplexer (MUX) circuit using multiple 2-to-1 MUXes, each built with tri-state drivers. Petitioner argued that while Pixley’s figures illustrated a single-bit implementation, a person of ordinary skill in the art (POSITA) would have found it obvious to adapt this design for multi-bit data words, a common requirement in digital circuit design.

      Watanabe provided the basis for this modification, explicitly teaching that an m-bit 2-to-1 multiplexer was known to be composed of m one-bit multiplexers. Petitioner contended that a POSITA would have found it obvious to implement Pixley’s circuit as an m-bit multiplexer by "stacking" m instances of Pixley’s one-bit circuit. This scaled-up circuit would inherently multiplex a "plurality of data words" as required by the claims.

      Petitioner mapped the limitations of independent claim 1 directly to this combined art. Pixley’s nested MUX circuit (FIG. 9) provided the claimed "first stage logic" (e.g., MUX 116) and "second stage logic" (e.g., MUX 112). Each MUX in Pixley was shown to contain the requisite "tristate drivers" (a second and third tristate driver for the second stage logic) configured to select and transmit data based on select signals. The combination of Pixley and Watanabe thus disclosed a complete circuit for multiplexing data words using first and second stage logic composed of tristate drivers.

      The arguments for other independent and dependent claims built upon this foundation. For claim 3, which added transmitting the selected data word to a "system bus," Petitioner argued Watanabe taught using such multiplexer configurations to read an operand from a register and send it to an arithmetic and logical unit (ALU) via a system bus. For claim 7, which required latch circuits, Petitioner argued that a POSITA would have been motivated to use latches (or D flip-flops, which contain latches and are mentioned in Pixley) to implement a synchronous, clock-based system, which was a well-known and often necessary design choice for ensuring orderly operation. For claim 20, which required a "third data word" and "third stage logic," Petitioner argued that Watanabe's disclosure of cascading multiplexers to handle more than four data inputs would have made it obvious to extend Pixley's two-stage nested design to a third stage.

    • Motivation to Combine: A POSITA would combine Pixley and Watanabe to solve a common and well-understood engineering problem: adapting a known circuit design for use in practical, multi-bit processing applications. Pixley provided a fundamental circuit architecture for a nested, tri-state MUX, while Watanabe provided the explicit, known method for scaling such one-bit circuits to handle the m-bit data words used in processors and other digital systems. The motivation was to apply a standard design principle (scaling) to a known circuit element to achieve a desired, predictable functionality.

    • Expectation of Success: The combination of Pixley and Watanabe involved applying conventional design techniques to known circuit elements. A POSITA would have had a high expectation of success in stacking Pixley’s one-bit MUX circuits to create a functional m-bit MUX, as this was a standard and predictable method for scaling digital logic circuits.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-21 of the ’448 patent as unpatentable.