BOE Technology Group Co Ltd v. Samsung Display Co Ltd

1. Case Identification

• Case #: IPR2025-01499
• Patent #: 9,299,730
• Filed: August 31, 2025
• Petitioner(s): BOE Technology Group Co., Ltd.
• Patent Owner(s): Samsung Display Co., Ltd.
• Challenged Claims: 1-19

2. Patent Overview

• Title: TFT Array Substrate and Organic Light Emitting Display
• Brief Description: The ’730 patent discloses a thin film transistor (TFT) array substrate for an Organic Light-Emitting Diode (OLED) display. The invention focuses on a storage capacitor structure where an upper electrode is arranged to overlap with the entire lower electrode to maintain a substantially constant capacitance despite overlay deviations during manufacturing, thereby preventing display defects.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ishii100 and Ishii423 - Claims 1 and 2 are obvious over Ishii100 in view of Ishii423.

• Prior Art Relied Upon: Ishii100 (Application # 2007/0058100) and Ishii423 (Application # 2008/0186423).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ishii100, which addresses decreasing capacitor area due to manufacturing mask margins, discloses nearly all limitations of claim 1. Specifically, Ishii100 teaches a TFT array substrate with a capacitor having an upper electrode (capacitor line 300) that overlaps and extends beyond a lower electrode (relay layer 71) and includes an opening for a self-aligning contact hole. To the extent Ishii100 does not fully teach the "connection node" coupling the lower electrode to a TFT, Petitioner asserted that Ishii423 explicitly discloses this feature. Ishii423 teaches using a relay layer (93) on an interlayer insulating film to electrically couple a lower capacitor electrode to a pixel electrode and TFT through contact holes.
  • Motivation to Combine: A POSITA would combine these references because they share the same inventor, are in the same field of electro-optical devices, and address the same technical problem of improving display image quality. Ishii423's use of a relay layer for a more reliable electrical connection would have been seen as a straightforward and advantageous modification to the similar device structure in Ishii100.
  • Expectation of Success: Given the significant structural similarities between the devices in Ishii100 and Ishii423 and their common objective, a POSITA would have had a high expectation of success in combining their teachings to improve image quality.

Ground 2: Obviousness over Park, Ishii100, and Kwon - Claims 6-9 and 15-19 are obvious over the combination of Park and Ishii100, further in view of Kwon.

• Prior Art Relied Upon: Park (Application # 2003/0141811), Ishii100 (Application # 2007/0058100), and Kwon (Application # 2002/0118150).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that the combination of Park and Ishii100 renders obvious the base claims upon which claims 6-9 depend. Park discloses an active matrix OLED device with a pixel circuit, and Ishii100 teaches features like a self-alignment contact hole to increase capacitance. This combination, however, may not explicitly teach the "compensation TFT" recited in claim 6. Petitioner argued that Kwon remedies this deficiency. Kwon is directed to an OLED display that compensates for threshold voltage (VTH) deviations in the driving TFT. Kwon explicitly teaches a "compensation transistor" (M2) coupled to the driving transistor (M1) to compensate for such deviations, directly mapping to the limitations of claim 6. Kwon further teaches forming the compensation gate electrode from the same layer as the lower capacitor electrode (claim 7) and using an initialization TFT (M4) to reset the driving gate's voltage in response to a previous scan signal (claims 8 and 9).
  • Motivation to Combine: A POSITA would combine Park/Ishii100 with Kwon because all three references address improving performance in OLED pixel circuits. A POSITA, having designed a pixel circuit according to Park and Ishii100, would have recognized the well-known problem of VTH variation and would have been motivated to incorporate a known solution, such as the compensation circuit taught by Kwon, to improve gray scale performance and display uniformity.
  • Expectation of Success: The technique of using compensation transistors was a known solution to a known problem in the art. A POSITA would have reasonably expected to successfully integrate Kwon's standard compensation and initialization circuitry into the pixel layouts of Park and Ishii100.

Ground 3: Obviousness over Liu and Ono - Claims 1-6, 8, and 10-19 are obvious over Liu in view of Ono.

• Prior Art Relied Upon: Liu (Application # 2012/0313100) and Ono (Application # 2011/0128211).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued Liu discloses a pixel structure with most of the claimed elements, including a capacitor with a lower electrode (E3) and an overlapping upper electrode (E2). However, to the extent Liu does not explicitly teach the upper electrode having an "opening," Petitioner contended that Ono provides this teaching. Ono addresses the problem of limited pixel space by teaching the formation of a capacitor directly over the driving transistor, thereby increasing design flexibility. Petitioner argued it would have been obvious to a POSITA to modify Liu's upper electrode to include an opening to accommodate the space-saving layout taught by Ono and for routing connections.
  • Motivation to Combine: A POSITA would combine Liu and Ono because both address the efficient use of space in a pixel structure to miniaturize OLED devices and/or increase storage capacitance. Ono teaches using the area above a driving transistor to form a capacitor. A POSITA looking to optimize the pixel layout of Liu, which had unoccupied space above its driving transistor, would have been motivated to apply Ono's technique to increase the capacitor area without increasing the overall pixel footprint.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success in applying Ono's space-saving capacitor layout to Liu's pixel structure. The combination would not require new layers or complex process changes, but would instead utilize existing unoccupied space, making it a predictable and straightforward modification to improve device performance.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including Ground 1 (Claims 1-2 over Ishii100 alone) and Ground 3 (Claims 3-5, 10-14 over Park and Ishii100), which relied on similar teachings and motivations as the grounds detailed above.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not deny institution under §325(d) because none of the prior art references relied upon in the petition were previously presented to or considered by the USPTO during the prosecution of the ’730 patent. Petitioner contended the asserted art is materially different from the prosecution art, as it teaches the key limitation of an upper capacitor electrode overlapping the whole lower electrode, which the Examiner previously found lacking in the art of record.
• Petitioner also argued against discretionary denial under Fintiv, stating that a Final Written Decision (FWD) would issue well before any potential trial date in the parallel district court litigation, for which no schedule had yet been set.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-19 of Patent 9,299,730 as unpatentable.