BOE Technology Group Co., Ltd. v. Samsung Display Co., Ltd.

1. Case Identification

• Case #: IPR2025-01499
• Patent #: 9,299,730
• Filed: August 31, 2025
• Petitioner(s): BOE TECHNOLOGY GROUP CO., LTD.
• Patent Owner(s): SAMSUNG DISPLAY CO., LTD.
• Challenged Claims: 1-19

2. Patent Overview

• Title: TFT Array Substrate and OLED Display
• Brief Description: The ’730 patent discloses a thin film transistor (TFT) array substrate for an Organic Light-Emitting Diode (OLED) display. The invention focuses on a storage capacitor structure where an upper electrode is arranged to overlap with the entire lower electrode, aiming to maintain a substantially constant capacitance even when manufacturing mask misalignments (overlay deviation) occur.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 2 are obvious over Ishii100.

• Prior Art Relied Upon: Ishii100 (Application # 2007/0058100).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Ishii100 discloses all elements of claims 1 and 2. Ishii100 teaches a TFT array substrate with a storage capacitor (70) designed to increase capacitor area and account for mask alignment margins. Petitioner mapped Ishii100’s relay layer (71) as the claimed “lower electrode” and its capacitor line (300) as the claimed “upper electrode.” Ishii100’s figures show the upper electrode overlapping and extending beyond the lower electrode. The reference also discloses an opening (850) through various insulating films that provides for a self-alignment-type contact hole (85), which serves as the claimed “node contact hole.” For dependent claim 2, Petitioner asserted that Ishii100’s figures show the opening (850) overlaps with the lower electrode (71), as the opening is etched through layers to expose the lower electrode.
  • Motivation to Combine (for §103 grounds): As this ground relies on a single reference, Petitioner argued that all claim elements were present in Ishii100 or would have been obvious modifications. Petitioner contended it was known at the time of the invention to make the upper electrode larger than the lower electrode to prevent capacitance changes resulting from overlay deviation.

Ground 2: Claims 3, 4, 5, and 10-14 are obvious over Park in view of Ishii100.

• Prior Art Relied Upon: Park (Application # 2003/0141811) and Ishii100 (Application # 2007/0058100).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Park, which discloses an active matrix OLED display, teaches the foundational pixel circuit, including a storage capacitor (Cst1) with a lower electrode (gate electrode 122) and an upper electrode (capacitor electrode 152). Park’s structure shows the upper electrode overlapping the lower electrode. Ishii100 was argued to supply the remaining limitations not explicitly taught by Park, specifically an opening in the upper electrode and a self-alignment-type contact hole. The combination of Park’s OLED pixel structure with Ishii100’s capacitor and contact hole design was alleged to render the claims obvious. For claim 5, Park was argued to teach a driving TFT whose gate electrode (122) is also the lower electrode of the capacitor, thus overlapping.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Park and Ishii100 because both references address the problem of increasing storage capacitance in light-emitting display devices. Petitioner argued a POSITA would be motivated to incorporate Ishii100’s self-alignment-type contact hole into Park’s design to increase the storage capacitor area and reduce manufacturing complexity by eliminating a mask step, a known benefit taught by Ishii100.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because the references describe similar circuit structures and address analogous problems in the same field of endeavor.

Ground 3: Claims 1-6, 8, and 10-19 are obvious over Liu in view of Ono.

• Prior Art Relied Upon: Liu (Application # 2012/0313100) and Ono (Application # 2011/0128211).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued Liu discloses a pixel structure for an OLED display with a capacitor (CS) formed from multiple electrodes (E1, E2, E3) and insulating layers. Liu’s figures were asserted to show an upper electrode (E2) overlapping and extending beyond lower electrodes (E1, E3). To the extent Liu does not explicitly teach an "opening" in the upper electrode, Petitioner argued Ono supplies this feature. Ono teaches forming a capacitor over the driving transistor to increase design flexibility and make efficient use of pixel space. The combination results in a structure where Liu's upper electrode is extended over a driving transistor (as taught by Ono), and an opening would be an obvious design choice to accommodate connections.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Liu and Ono because both address the miniaturization of OLED devices by using pixel space more efficiently. Liu's pixel layout includes unoccupied space above the driving transistor. Petitioner argued a POSITA would be motivated to apply Ono’s technique of forming a capacitor in this unused space to increase the total capacitance of Liu’s pixel without enlarging its footprint.
  • Expectation of Success (for §103 grounds): The combination was argued to have a high expectation of success as it utilizes known techniques to improve device performance by modifying an existing layout without adding new manufacturing layers, a straightforward modification for a POSITA.

• Additional Grounds: Petitioner asserted that claims 1 and 2 are obvious over Ishii100 in view of Ishii423 (Application # 2008/0186423). Petitioner also asserted additional obviousness challenges for claims 6-9 and 15-19 based on the combination of Park, Ishii100, and Kwon (Application # 2002/0118150), which introduces a compensation TFT to address threshold voltage variations.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under Fintiv because a Final Written Decision in this IPR would issue before any trial in the corresponding district court litigation, for which a schedule had not yet been set.
• Petitioner also argued against denial under 35 U.S.C. §325(d), contending that none of the prior art references asserted in the petition were considered during the original examination of the ’730 patent. Petitioner asserted the new art is materially different from the prosecution art and teaches key claim limitations, such as an upper electrode overlapping the entire lower electrode, which the Examiner previously had not considered.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-19 of Patent 9,299,730 as unpatentable.