Micron Semiconductor Products Inc v. Palisade Technologies LLP

1. Case Identification

• Case #: IPR2025-01560
• Patent #: 8,996,838
• Filed: October 14, 2025
• Petitioner(s): Micron Technology, Inc., and Micron Semiconductor Products, Inc.
• Patent Owner(s): Palisade Technologies, LLP
• Challenged Claims: 1-3, 8, 11-14, and 19-20

2. Patent Overview

• Title: Data Storage Device and Method of Operating Same
• Brief Description: The ’838 patent discloses methods and systems for operating 3D NAND flash memory devices. The technology addresses performance degradation caused by physical variations, such as tapering, in the memory’s vertical column structures by identifying, storing, and accessing information about the location where these structural variations begin.

3. Grounds for Unpatentability

Ground 1: Obviousness over Oh - Claims 1-2, 8, 11-13, and 19-20 are obvious over Oh.

• Prior Art Relied Upon: Oh (Application # 2012/0254680).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Oh taught all elements of the challenged claims. Oh disclosed a 3D nonvolatile memory with semiconductor pillars extending through stacked memory layers, where the pillars have a tapered profile (a structural variation). Oh addressed the resulting low data reliability by identifying a "bad area" and storing "bad area information." Petitioner contended this "bad area information," which identifies layers with low reliability caused by pillar width variations, corresponds directly to the ’838 patent’s "information identifying a location associated with a variation of the structure." Oh further disclosed storing this information in an address management register or memory cell array and subsequently accessing it to manage memory operations, thereby meeting the storing and accessing limitations of independent claims 1 and 12.
  • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
  • Expectation of Success (for §103 grounds): Not applicable (single reference ground).

Ground 2: Obviousness over Oh in view of Oh ’738 - Claims 1-2, 8, 11-13, and 19-20 are obvious over Oh in view of Oh ’738.

• Prior Art Relied Upon: Oh (Application # 2012/0254680) and Oh ’738 (Patent 8,730,738).
• Core Argument for this Ground:
  • Prior Art Mapping: To the extent Oh alone does not render the claims obvious, Petitioner argued the combination with Oh ’738 does. Oh taught identifying and storing information about general "bad areas" caused by structural variations. Oh ’738 disclosed a similar 3D memory structure but specifically taught using stacked "sub pillars" connected by semiconductor pads. Critically, Oh ’738 recognized that memory layers adjacent to these sub-pillar connection points are likely to be "dummy" or bad areas due to the abrupt structural change. Combining the references would involve applying Oh's method for detecting bad areas to the specific, predictable bad areas identified by Oh ’738 at sub-pillar junctions.
  • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine these references to improve memory device performance. Both references were directed to the same technology, shared the same inventors, and were assigned to the same entity (Samsung). A POSITA would have been motivated to apply Oh's general bad-area detection system to the specific, known source of unreliability (sub-pillar junctions) taught by Oh ’738 to proactively manage and avoid storing data in those known problematic locations.
  • Expectation of Success: A POSITA would have a high expectation of success because the references disclosed nearly identical memory structures. Implementing Oh's bad-area detection in the context of Oh '738's structure would have been a straightforward application of a known technique to a known problem area, resulting in an operable and improved device.

Ground 3: Obviousness over Tokiwa - Claims 1-3, 8, 11-14, and 19-20 are obvious over Tokiwa.

• Prior Art Relied Upon: Tokiwa (Patent RE47,866).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Tokiwa disclosed a 3D memory with tapered "columnar active layers," which caused variations in write speeds across different memory layers. To compensate, Tokiwa taught determining and storing layer-specific write potential information (e.g., voltages) in a register or memory array. Petitioner argued this stored information met the limitations of claims 1 and 12 because it identified a location (each memory layer), was associated with a structural variation (the taper at that layer), and was stored and accessed by a controller to adjust write operations. For claim 3, Petitioner argued Tokiwa’s "trimming processing," which determined suitable write potentials by judging write time against a predetermined period for each layer, met the claim's requirement of measuring and comparing parameters.
  • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
  • Expectation of Success (for §103 grounds): Not applicable (single reference ground).

• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) for all challenged claims based on Tokiwa in view of Oh ’738. The argument relied on a similar motivation to combine as in Ground 2, suggesting a POSITA would have modified Tokiwa’s compensation method to account for the specific structural variations introduced by the stacked sub-pillar structures taught in Oh ’738.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 8, 11-14, and 19-20 of the ’838 patent as unpatentable.