Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

1. Case Identification

• Case #: IPR2026-00061
• Patent #: 8,076,194
• Filed: December 5, 2025
• Petitioner(s): Taiwan Semiconductor Manufacturing Company Ltd.
• Patent Owner(s): Marlin Semiconductor Ltd.
• Challenged Claims: 1-22

2. Patent Overview

• Title: METHOD OF FABRICATING METAL OXIDE SEMICONDUCTOR TRANSISTOR
• Brief Description: The ’194 patent discloses a method for fabricating Metal Oxide Semiconductor (MOS) transistors, particularly for forming strained channels using epitaxial source/drain regions. The purportedly novel feature is a specific process sequence where an epitaxial layer is formed in a recess adjacent to the transistor gate before the formation of a sidewall spacer on the gate.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness over Hoentschel262 - Claims 1-22 are anticipated or obvious over Hoentschel262

• Prior Art Relied Upon: Hoentschel262 (Patent 7,579,262).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hoentschel262 teaches a nearly identical method for forming both PMOS and NMOS transistors with strained channels. It discloses using a "disposable spacer" to define the location for etching recesses, growing a strained semiconductor material (e.g., SiGe or SiC) in the recesses, removing the disposable spacer, and subsequently forming a final sidewall spacer structure. Critically, Hoentschel262 explicitly discloses that the epitaxial growth process can involve "any desired degree of... overfilling," which would result in a raised epitaxial layer extending above the substrate surface, as required by independent claims 1 and 10. For dependent claims, Hoentschel262 discloses or suggests using silicon nitride for the disposable spacer (claim 3/12), provides a thickness range (3-50 nm or 30-500 angstroms) that fully encompasses the claimed range of 150-250 angstroms (claim 4/13), and teaches forming source/drain regions after the final spacer is in place (claim 7).
  • Motivation to Combine (for §103 grounds): To the extent any limitation was not explicitly disclosed, a person of ordinary skill in the art (POSITA) would have found it obvious to implement them. For example, a POSITA would have been motivated to use the "overfilling" technique to create raised epitaxial regions, as this was a well-known method to improve performance by increasing strain transfer and reducing contact resistance. Similarly, using common materials like silicon nitride and conventional structures like an oxide liner/nitride spacer pair was a standard practice for predictable results.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in applying these well-known techniques and materials within the Hoentschel262 framework, as they were routine modifications in semiconductor fabrication intended to achieve known benefits.

Ground 2: Anticipation and Obviousness over Wang753 - Claims 1-3, 5-12, 14-16, 21, and 22 are anticipated or obvious over Wang753

• Prior Art Relied Upon: Wang753 (Patent 7,449,753).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Wang753 anticipates every limitation of the challenged claims. Wang753 describes fabricating PMOS and NMOS devices that include raised SiGe stressors, gate stacks, and multi-layer spacers. The method involves forming recesses using a disposable "dummy layer," growing epitaxial SiGe stressors that explicitly extend above the substrate surface, removing the dummy layer, and then forming final spacers that contact a portion of the raised epitaxial stressors. This process directly maps to the sequence in independent claims 1 and 10. Wang753 further discloses using a protective layer comprising silicon nitride (claim 3/12), final spacers comprising an oxide liner and nitride layer (claim 5/14), and the formation of lightly doped drain (LDD) regions adjacent to the gate (claim 8/11).
  • Motivation to Combine (for §103 grounds): For any claim element deemed not explicitly disclosed, a POSITA would have found it obvious to incorporate. The teachings in Wang753 are presented as standard fabrication processes for advanced transistors. A POSITA would understand from the figures and text that the described structures and steps were conventional and could be implemented as claimed to achieve the desired transistor performance.
  • Expectation of Success (for §103 grounds): The detailed process flows and resulting structures shown in Wang753 would have provided a POSITA with a clear roadmap and a reasonable expectation of success in fabricating the claimed transistor.

Ground 3: Obviousness over Hoentschel262 in view of Wang407 - Claims 5, 7-9, 11, 14, and 17-20 are obvious over Hoentschel262 and Wang407

• Prior Art Relied Upon: Hoentschel262 (Patent 7,579,262) and Wang407 (Patent 7,605,407).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground asserted that Hoentschel262 provides the foundational fabrication method, while Wang407 provides specific, well-known implementation details for features recited in the dependent claims. For example, claims 5 and 14 require a spacer with an "oxide liner and a nitride spacer." While Hoentschel262 teaches multi-element spacers, Wang407 explicitly discloses this common oxide/nitride structure for the same purpose of defining doping profiles.
  • Motivation to Combine (for §103 grounds): A POSITA implementing the process of Hoentschel262 would combine its teachings with Wang407 to optimize the spacer structure and doping profiles. Both references are analogous art focused on improving MOS device performance with epitaxial stressors. A POSITA would look to Wang407 for established techniques, such as using a liner oxide for adhesion and protection, and a nitride layer for its etch selectivity, to implement Hoentschel262’s more general disclosure of a "sidewall spacer structure."
  • Expectation of Success (for §103 grounds): A POSITA would have expected success, as this combination merely involved applying a conventional spacer design from Wang407 into the analogous process flow of Hoentschel262 to achieve predictable improvements in device fabrication and performance.
• Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 4 and 13 based on the combined teachings of Wang753 and Hoentschel262.

4. Key Claim Construction Positions

• "offset spacer" (claims 6 and 15): Petitioner noted the claim language "spacer further comprises an offset spacer, positioned between [the] gate and [the] spacer" is potentially ambiguous. For the purpose of its invalidity analysis, Petitioner adopted an interpretation where the "offset spacer" is one layer of a multi-layer spacer structure that is positioned between another layer of that same spacer structure and the gate.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-22 of Patent 8,076,194 as unpatentable.