PTAB

IPR2026-00066

Taiwan Semiconductor Mfg Co Ltd v. MYW Semitech LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Chip Package
  • Brief Description: The ’763 patent relates to semiconductor chip packages featuring a solid layer (e.g., an interposer or molding compound) with through-vias for vertical connections. The architecture includes interconnection schemes, such as redistribution layers (RDLs), formed on the surfaces of the solid layer to route signals to and from semiconductor chips.

3. Grounds for Unpatentability

Ground 1: Claims 1-12, 14, 16-21, and 23 are obvious over Sundaram in view of Lin-191

  • Prior Art Relied Upon: Sundaram (Patent 9,167,694) and Lin-191 (Application # 2010/0290191).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sundaram disclosed the foundational structure of the challenged claims, including a chip package with a glass interposer (a solid layer) having through-vias filled with copper plugs. Sundaram further taught polymer-metal redistribution layers (a first interconnection scheme) on the interposer’s surface to connect stacked memory ICs (a first semiconductor chip). To meet limitations not explicitly taught by Sundaram, Petitioner asserted that Lin-191 supplied teachings for conventional features. Specifically, Lin-191 was cited for its disclosure of metal bumps comprising a second metal layer (an under-bump metallurgy or UBM layer) and an overlying tin-containing solder layer. Lin-191 also taught the use of standard aluminum metal pads on semiconductor chips for interconnection.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Lin-191’s teachings with Sundaram’s package to improve performance and manufacturability using well-known techniques. A POSITA would have been motivated to apply Lin-191’s layered bump structure to Sundaram’s copper bumps to improve the mechanical strength and reliability of the interconnects. Similarly, since connecting chips requires metal pads, a POSITA would have found it obvious to incorporate the ubiquitous aluminum pads taught by Lin-191 onto the semiconductor chips in Sundaram’s design.
    • Expectation of Success: A POSITA would have had a high expectation of success because the combination involved applying known, commonplace elements (UBM layers, solder caps, aluminum pads) to a known semiconductor package (Sundaram) to achieve the predictable results of improved reliability and standard interconnect functionality. The manufacturing techniques involved were routine in the industry.

Ground 2: Claims 1-5, 7-12, 14-15, and 17 are obvious over Yu in view of Lin-191

  • Prior Art Relied Upon: Yu (Patent 9,123,763) and Lin-191 (Application # 2010/0290191).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Yu provided an alternative foundational chip package architecture. Yu taught a package where a semiconductor die is encased in a molding compound (a solid layer) with through-mold vias (TMVs) acting as copper plugs. Yu also disclosed front-side and back-side interconnection schemes (RDLs) for electrically coupling various components. For certain dimensional limitations, Petitioner turned to Lin-191. For instance, Petitioner argued that while Yu disclosed a molding compound, Lin-191 taught an encapsulating layer with a thickness range of 20-500 micrometers, which rendered the claimed range of 100-300 micrometers obvious. Lin-191 was also cited for its teachings on integrating passive components (e.g., capacitors) into a package via solder joints on an interconnection scheme.
    • Motivation to Combine: A POSITA would combine Lin-191 with Yu to optimize the package’s physical and electrical properties. A POSITA would have been motivated to apply Lin-191’s disclosed thickness to Yu’s molding compound to achieve beneficial stress buffering, a known consideration for embedded chip architectures. Furthermore, to improve signal integrity—a constant goal in package design—a POSITA would have been motivated to incorporate the passive components taught by Lin-191 into Yu’s package to mitigate signal desynchronization.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in making these modifications. Adjusting the thickness of a molding layer was a matter of routine optimization, and incorporating passive components via soldering was a standard, well-established industry practice for improving electrical performance.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Sundaram and Lin-191 with references like Lin-863 (for a rectangular via region), Lin-691, or Shenoy (for a silver-containing seed layer). Further grounds combined Yu and Lin-191 with Sundaram (for stacked chip features) or Lin-863 to challenge the remaining claims based on similar theories of combining known elements for predictable results.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-23 of the ’763 patent as unpatentable.