PTAB

IPR2026-00067

Taiwan Semiconductor Mfg Co Ltd v. MYW Semitech LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Chip Package with Interposer and Stacked Dies
  • Brief Description: The ’306 patent discloses a semiconductor chip package architecture. The design centers on a solid interposer layer (e.g., glass or polymer) featuring metal posts in through-holes, which are used to vertically and horizontally connect multiple semiconductor chips and other components via one or more interconnection schemes.

3. Grounds for Unpatentability

Ground 1: Claims 1-7, 9-11, 13-15, and 17-27 are obvious over Sundaram in view of Lin-191

  • Prior Art Relied Upon: Sundaram (Patent 9,167,694) and Lin-191 (Application # 2010/0290191).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sundaram taught the core structure of the claimed chip package. This included an interconnect structure with a glass or polymer-glass interposer (the claimed solid layer), through-vias (the claimed metal posts), and polymer-metal redistribution layers (RDLs) forming an interconnection scheme. Sundaram also disclosed stacking electronic devices, such as memory chips, on the interposer. Petitioner asserted that Sundaram’s disclosed thickness range for the interposer (20-200 micrometers) overlaps with and renders obvious the claimed range of 50-150 micrometers, especially as the ’306 patent did not attribute any criticality to its specific range.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine the teachings of Lin-191 with Sundaram's framework to arrive at the claimed invention. The motivation was to incorporate known, beneficial features to improve Sundaram's design. Specifically, a POSITA would apply Lin-191’s teachings on layered metal bump structures (e.g., using an under-bump metallurgy (UBM) layer and a tin-containing solder cap) to improve the metallurgical bonding, strength, and fatigue resistance of Sundaram’s interconnects. Furthermore, a POSITA would modify Sundaram’s semiconductor chips to include metal pads as taught by Lin-191, as metal pads were a ubiquitous and essential technique for interconnecting chips to other components.
    • Expectation of Success: Petitioner argued that a POSITA would have had a high expectation of success. The proposed combination involved the application of known techniques (layered bumps, metal pads) to a known device (Sundaram's package) to achieve predictable improvements in performance and reliability. These modifications would have used well-known manufacturing processes common in the industry.

Ground 2: Claims 1-7, 9-15, 17-20, and 22-27 are obvious over Yu in view of Lin-191

  • Prior Art Relied Upon: Yu (Patent 9,123,763) and Lin-191 (Application # 2010/0290191).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Yu disclosed a Package-on-Package (PoP) structure that taught the fundamental elements of the claimed invention. Yu’s package included a molding compound that served as the claimed solid layer, through-mold vias (TMVs) filled with copper that functioned as the claimed metal posts, and an RDL structure that constituted the first interconnection scheme. Yu also taught embedding and stacking multiple dies, including memory dies (the claimed semiconductor chips), within this structure.
    • Motivation to Combine: Petitioner argued a POSITA would have been motivated to modify Yu’s package with specific teachings from Lin-191 to enhance its functionality and reliability. For example, a POSITA would apply Lin-191's teachings on encapsulating layer thickness to Yu's molding compound to provide beneficial stress buffering for the embedded die. A POSITA would also have been motivated to modify Yu’s solid layer to include a silicon dioxide (SiO2) layer, as taught by Lin-191, to create a superior water vapor barrier and improve package reliability. The motivations to incorporate Lin-191’s layered bump structures and metal pads were the same as in the combination with Sundaram: to improve interconnect robustness and provide standard connection points.
    • Expectation of Success: Petitioner claimed an expectation of success because the combination represented the application of a known technique (e.g., Lin-191’s SiO2 layer) to a known device (Yu's package) to solve a known problem (moisture permeability) and yield predictable results. The manufacturing processes involved, such as chemical-vapor deposition for the SiO2 layer, were standard and disclosed in both references.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including grounds that combined Sundaram or Yu with Lin-191 and further added Lin-863 (Patent 9,679,863) or Camacho (Application # 2011/0215458). Lin-863 was primarily cited for its teaching of arranging posts in a rectangular region surrounding a central region. Camacho was cited for its teachings on connecting stacked chips using through-silicon-vias (TSVs) and metal pads on opposing surfaces of a chip.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-27 of the ’306 patent as unpatentable.