PTAB

IPR2026-00130

Taiwan Semiconductor Manufacturing Company Limited v. Marlin Semiconductor Ltd.

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device With Epitaxial Structure
  • Brief Description: The ’609 patent discloses a FinFET (fin field effect transistor) semiconductor device. The invention centers on an isolation structure that surrounds a fin structure and features a "first top surface" under the gate structure that is higher than a "second top surface" at the sides of the gate structure.

3. Grounds for Unpatentability

Ground 1: Claims 1-6 and 8-10 are anticipated or obvious over Xu

  • Prior Art Relied Upon: Xu (Patent 9,166,022).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Xu, which discloses FinFET device fabrication, anticipates or renders obvious every limitation of the challenged claims. Xu teaches a FinFET with a fin structure, a surrounding isolation structure, a gate, and an epitaxial structure. Critically, Xu discloses a process for recessing the isolation features using an etching process. Petitioner asserted this process inherently creates the key claimed feature: an isolation structure with a first top surface under the gate that is higher than a second top surface at the sides of the gate. For dependent claim 2, which requires a height difference of 100-250 Angstroms, Xu explicitly teaches recessing the isolation features "about 100 Å," a point within the claimed range.
    • Motivation to Combine (for §103 grounds): For claim 5, which requires a recess in the fin filled by an epitaxial structure, Petitioner argued it would have been obvious to combine two adjacent embodiments within Xu. Xu's second embodiment teaches forming such a recess, while its first embodiment teaches forming an epitaxial structure. A POSITA would combine these teachings because Xu itself suggests combining features from its various embodiments to optimize transistor strain and performance, which is a known benefit of the recess-and-fill technique.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in combining Xu's embodiments, as the combination involved applying conventional and well-understood fabrication steps to achieve predictable improvements in device performance.

Ground 2: Claims 1, 3, 5, 6, and 8-10 are anticipated or obvious over Ching

  • Prior Art Relied Upon: Ching (Patent 9,281,378).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner presented Ching as an alternative primary reference that also discloses all limitations of the base claims. Ching describes a FinFET fabrication process where Shallow Trench Isolation (STI) regions are recessed. Ching explicitly states that in the resulting device, the STI surfaces at the sides of the gate can be "lower than" the STI surface underlying the gate, directly teaching the core limitation of claim 1. Petitioner further mapped how Ching discloses forming recesses at the end of the fin structure and filling them with epitaxial material (claims 5 and 6), using materials like silicon germanium (claim 8), and employing a replacement metal gate process (claim 3).

Ground 3: Claim 7 is obvious over Xu in view of Huang

  • Prior Art Relied Upon: Xu (Patent 9,166,022), Huang (Patent 8,809,139).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that the combination of Xu’s embodiments, as argued for claim 6, results in a structure where the bottom surface of the epitaxial structure is shallower than the bottom surface of the isolation structure. However, Xu does not disclose a specific numerical range for this height difference, as required by claim 7 (100-250 Angstroms). Huang was introduced to supply this missing dimensional teaching, as it discloses specific fin recess depths and resulting height differences in FinFETs. The dimensional range for this height difference disclosed in Huang (5 nm to 475 nm, or 50 to 4,750 Angstroms) fully encompasses the range claimed in the ’609 patent.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Huang’s dimensional teachings with Xu's device structure to optimize a known design parameter. As both references address the industry-wide goal of scaling down FinFETs, a POSITA would have looked to a reference like Huang for concrete dimensional guidance to control strain and improve packing density in the device taught by Xu.
    • Expectation of Success (for §103 grounds): Success was expected because combining the references merely involved applying known dimensional parameters from Huang to the result-effective variables (e.g., etch depth) of the conventional fabrication processes described in Xu.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 2 and 4 are obvious over Ching in view of Xu (to supply a specific height difference and a direct-contact feature via process reordering) and that claim 7 is obvious over Ching in view of Huang (to supply the specific bottom-surface height difference range).

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-10 of the ’609 patent as unpatentable.