PTAB

IPR2026-00130

Taiwan Semiconductor Manufacturing Company Limited

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1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device With Epitaxial Structure
  • Brief Description: The ’609 patent describes a FinFET (fin field effect transistor) semiconductor device. The invention centers on an isolation structure that surrounds a fin structure and has a stepped profile, wherein the portion of the isolation structure under the gate has a "first top surface" that is higher than the "second top surface" of the isolation structure at the sides of the gate.

3. Grounds for Unpatentability

Ground 1: Anticipation/Obviousness over Xu - Claims 1-6 and 8-10 are anticipated or obvious over Xu.

  • Prior Art Relied Upon: Xu (Patent 9,166,022).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Xu, which describes a FinFET device and manufacturing method, discloses every limitation of the challenged claims. Xu teaches forming a fin structure, a surrounding isolation structure, a gate, and an epitaxial layer. Crucially, Xu describes an etching process that selectively recesses the isolation features, which inherently creates a height difference where the isolation surface under the gate is higher than the surface at the sides of the gate, thus meeting the core limitation of claim 1. For dependent claim 2, Xu explicitly discloses recessing the isolation features "about 100 Å," a value that falls within the claimed range of 100-250 Å. For claim 5, which requires a recess at the end of the fin filled by the epitaxial structure, Petitioner contended it would be obvious to combine two disclosed embodiments within Xu to achieve this structure.
    • Motivation to Combine (for §103 grounds): For the combination of embodiments within Xu to meet claim 5, Petitioner asserted that Xu itself suggests combining steps from its different embodiments. A person of ordinary skill in the art (POSITA) would be motivated to combine the recess-and-fill technique of Xu's second embodiment with its first embodiment to control channel strain and optimize device performance, a benefit explicitly taught by Xu.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in combining Xu's embodiments, as Xu discloses conventional etch processes and the combination yields the predictable result of providing different starting substrates to achieve varying types of strain.

Ground 2: Obviousness over Xu in view of Huang - Claim 7 is obvious over Xu in view of Huang.

  • Prior Art Relied Upon: Xu (Patent 9,166,022), Huang (Patent 8,809,139).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Xu's embodiments (as argued in Ground 1) teaches all limitations of claim 6, including an epitaxial structure in a fin recess where its bottom surface is shallower than the isolation structure's bottom surface. However, Xu does not provide specific numerical values for this height difference. Huang, which also describes FinFET fabrication, provides the missing dimensional guidance. Huang discloses fin recess depths that result in a height difference between the epitaxial structure and isolation structure bottom surfaces ranging from 5 nm to 475 nm (50 Å to 4,750 Å), a range that completely encompasses the 100-250 Å range required by claim 7.
    • Motivation to Combine (for §103 grounds): A POSITA, seeking to implement Xu’s method, would combine its teachings with Huang's specific dimensions as a matter of routine optimization. Both references address the same technical field and the industry-wide goal of device scaling. Huang provides a known, workable range for a results-effective variable (recess depth) that Xu teaches should be controlled to optimize performance.
    • Expectation of Success (for §103 grounds): A POSITA would expect to successfully apply Huang's dimensional teachings to Xu's process, as the claimed range lies within a desirable portion of Huang's disclosed range, corresponding to smaller device dimensions that improve packing density and performance.

Ground 3: Anticipation/Obviousness over Ching - Claims 1, 3, 5, 6, 8-10 are anticipated or obvious over Ching.

  • Prior Art Relied Upon: Ching (Patent 9,281,378).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Ching independently discloses a FinFET structure that meets the limitations of the challenged claims. Ching explicitly states that in its resulting FinFET, the isolation (STI) regions on opposite sides of the gate can have top surfaces that are "lower than" the top surface of the STI region underlying the gate, directly teaching the key structural limitation of claim 1. Ching also teaches all other primary features, including forming recesses at the ends of the fin structure and filling those recesses with epitaxially grown material (e.g., silicon germanium) to form source and drain regions.
  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 2 and 4 are obvious over Ching in view of Xu, and claim 7 is obvious over Ching in view of Huang, relying on similar motivations to combine for dimensional guidance and process optimization.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-10 of the ’609 patent as unpatentable.