PTAB

IPR2026-00151

Citadel Securities LLC v. HFT Solutions LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Field Programmable Gate Array with External Phase Controller
  • Brief Description: The ’381 patent describes a method for processing data in a field programmable gate array (FPGA) system. The method uses an external phase-locked loop (PLL) to synchronize a receiver-side clock with a transmitter-side clock, allegedly to avoid the latency associated with conventional on-chip clock domain crossing circuits.

3. Grounds for Unpatentability

Ground 1: Anticipation by Altera - Claims 1, 4, and 6-10 are anticipated by Altera under 35 U.S.C. §102.

  • Prior Art Relied Upon: Altera (a 2015 white paper titled "Synchronous Ethernet Solutions with Altera FPGAs and Silicon Labs Jitter-Attenuating PLLs"), supported by extrinsic evidence from the Stratix Handbook and the Si5345 Manual.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Altera, a white paper describing a reference design, discloses every limitation of the challenged claims. The Altera system uses an Altera Stratix V FPGA interoperating with an external Silicon Labs Si5345 PLL for high-performance clock synchronization in Ethernet networking. Petitioner asserted that a person of ordinary skill in the art (POSA) would understand that the inherent features of the specific, off-the-shelf components named in Altera (the Stratix FPGA and Si5345 PLL) are necessarily present in the described system. The petition used the Stratix Handbook and Si5345 Manual as extrinsic evidence to demonstrate these inherent features. Altera’s system receives serial data, uses its FPGA’s receiver blocks (deserializer) to generate a recovered clock signal and parallel data, and transmits the recovered clock to the external Si5345 PLL. The external PLL generates a stabilized second clock signal that is used to create a transmitter-side clock within the FPGA, thereby synchronizing the system without needing latency-inducing clock domain crossing circuits.

Ground 2: Obviousness over Altera and Lockwood - Claims 1-4 and 6-12 are obvious over Altera in view of Lockwood under 35 U.S.C. §103.

  • Prior Art Relied Upon: Altera (the 2015 white paper) and Lockwood (a 2012 paper titled "A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Altera teaches a complete hardware solution for low-latency clock synchronization using an FPGA and an external PLL. Lockwood teaches the critical importance of minimizing latency in high-frequency trading (HFT) and describes implementing trading algorithms on FPGAs to achieve the lowest possible processing times. The combination of Altera’s low-latency synchronization method with Lockwood’s HFT application renders the claims obvious. Specifically, applying Altera's system to the HFT context taught by Lockwood would make the "market data" and "trading algorithm" limitations of claims 2 and 3 obvious.
    • Motivation to Combine: A POSA in the HFT field would have been motivated to combine the teachings. Lockwood emphasized that minimizing latency is paramount for profitability in HFT. Altera’s solution directly addresses latency by eliminating clock domain crossing circuits. A POSA would therefore have recognized Altera’s technique as an attractive and obvious solution to apply to the HFT systems described by Lockwood to gain a competitive advantage.
    • Expectation of Success: A POSA would have had a high expectation of success. FPGAs are inherently programmable, making it straightforward to implement the financial processing logic and trading algorithms described by Lockwood onto the computational fabric of the Altera system. The combination involved applying a known low-latency hardware solution to an industry expressly focused on reducing latency.

Additional Grounds: Petitioner asserted an alternative obviousness challenge to claims 1, 4, and 6-10 based on the combination of Altera, the Stratix Handbook, and the Si5345 Manual, arguing that if the features of the handbooks are not considered inherent in Altera, it would have been obvious to combine them as they describe the specific components Altera directs a user to combine.

4. Key Claim Construction Positions

  • For the purposes of the IPR, Petitioner stated it adopted the plain and ordinary meaning of the claim terms.
  • "deserializer": Petitioner explicitly adopted the ’381 patent's specification description, where the "deserializer" may comprise a receiver Physical Medium Attachment (PMA) and a receiver Physical Coding Sublayer (PCS), to map limitations onto the prior art.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §314(a) would be inappropriate. The petition asserted that the co-pending district court litigation is in its infancy, with no deadlines set or discovery completed, minimizing any potential overlap or inefficiency.
  • Petitioner also argued that denial under §325(d) is unwarranted because the primary prior art references, particularly the Altera white paper, were not before the examiner during prosecution. Petitioner contended these references are highly material and present a much stronger case for unpatentability than the art considered by the USPTO, which did not result in any anticipation or obviousness rejections.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-4 and 6-12 of the ’381 patent as unpatentable.