PTAB

IPR2026-00193

Amazon.com Inc v. InterDigital Inc

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Methods and Apparatus for Signaling Intra Prediction for Large Blocks for Video Encoders and Decoders
  • Brief Description: The ’876 patent discloses technology for video encoding and decoding that expands upon the H.264 standard by using large blocks (e.g., 64x64) that can be hierarchically partitioned. The invention focuses on methods for signaling intra prediction for these large blocks by defining a "basic coding unit" size and using hierarchical "split signaling" syntax to indicate whether a block is split into smaller sub-blocks.

3. Grounds for Unpatentability

Ground 1: Claims 1-8 and 11-18 are obvious over Xiong in view of VCEG-AJ21.

  • Prior Art Relied Upon: Xiong (WO 2008/083633) and VCEG-AJ21 (a publicly available technical contribution from October 2008).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combined teachings disclosed all limitations of the independent claims. Xiong taught a method for intra-frame prediction that organizes video blocks in a hierarchical tree, including for macroblocks larger than 16x16 (e.g., 32x32). Xiong's syntax table used a binary flag (e.g., ext_16x16_pred_flag) to signal whether a block should be partitioned into four smaller sub-blocks (if the flag is 0) or if a single prediction mode applies to the entire block (if the flag is 1). Petitioner contended this flag met the limitation for a "binary split signaling syntax element." VCEG-AJ21 explicitly proposed extending the H.264 video coding architecture to use even larger macroblock sizes (e.g., 32x32, 64x64, and 128x128) for improved efficiency. The combination of Xiong's hierarchical signaling with VCEG-AJ21's larger block sizes allegedly taught a method for a "large block" (≥32x32) that is larger than a "basic coding unit" (16x16), and using a binary signal to partition it. Further, Petitioner argued that Xiong's ext_16x16_pred_flag, when set to 1, indicates an intra partition type of 16x16, thereby meeting the limitation for a "second syntax element indicating a single spatial intra partition type."
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the references to improve video compression performance. Both references explicitly built upon the H.264 standard and sought to improve it by using larger macroblocks. A POSITA would have been motivated to apply Xiong’s efficient hierarchical signaling and syntax structure to the larger block sizes disclosed in VCEG-AJ21 to achieve the "enhanced coding efficiency for high resolution video" that VCEG-AJ21 identified as a key benefit.
    • Expectation of Success: Petitioner asserted that a POSITA would have had a reasonable expectation of success because expanding Xiong's system was a matter of routine engineering. The hierarchical structure and related syntax could be easily scaled to larger block sizes by replicating existing code or using recursive functions to address each level of the hierarchy (e.g., creating an ext_64x64_pred_flag based on Xiong's ext_16x16_pred_flag).

Ground 2: Claims 9-10 are obvious over Xiong, VCEG-AJ21, and H.264.

  • Prior Art Relied Upon: Xiong (WO 2008/083633), VCEG-AJ21, and H.264 (ITU-T Recommendation H.264, Nov. 2007).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground added H.264 to address the limitations in apparatus claims 9 and 10 concerning pre-stored or received prediction mode tables. For claim 9 (pre-stored table), Petitioner argued that H.264's Table 7-11 is a pre-stored intra prediction mode table implemented in firmware. A decoder uses this table to look up the correct prediction mode (Intra16x16PredMode) based on a received syntax element (mb_type), thus using a pre-stored table to decode picture data. For claim 10 (received table), Petitioner asserted that H.264 disclosed a mechanism using high-level syntax elements (seq_scaling_matrix_present_flag and scaling_list) to transmit custom scaling matrices from an encoder to a decoder. Petitioner contended these matrices are analogous to an intra prediction mode table and are used by the decoder to process blocks, thus meeting the limitation of receiving such a table.
    • Motivation to Combine: A POSITA implementing the larger block sizes from the Xiong/VCEG-AJ21 combination would naturally look to the underlying H.264 standard for implementation details like prediction mode tables. It would have been a simple and logical step to extend H.264's existing table-based architecture to accommodate the new, larger partition types, rather than inventing an entirely new system. This would maintain compatibility and leverage a well-understood framework.
    • Expectation of Success: A POSITA would have expected success in supplementing the H.264 tables with additional rows for the larger partition types (e.g., 32x32, 64x64) taught by the primary combination. This was a straightforward extension of a known and documented standard.

4. Key Claim Construction Positions

  • Petitioner argued that while no formal claim construction was necessary, the term "basic coding unit" should be understood to at least encompass a 16x16 block. This interpretation is consistent with an embodiment in the ’876 patent and is important to Petitioner's argument that the 32x32 and larger blocks disclosed in the prior art meet the claim limitation of a "large block" being "greater than a size of a basic coding unit."

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-18 of the ’876 patent as unpatentable.