PTAB

IPR2026-00212

Citadel Securities LLC v. HFT Solutions LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Field Programmable Gate Array with External Phase-Locked Loop
  • Brief Description: The ’286 patent describes methods for low-latency data processing in a field programmable gate array (FPGA) system. The invention uses an external phase-locked loop (PLL) to synchronize receiver-side and transmitter-side clocks, which allegedly avoids the latency introduced by internal clock-domain crossing circuits commonly used in prior art FPGAs.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 8, 10-11, and 19 are anticipated by Altera under 35 U.S.C. §102.

  • Prior Art Relied Upon: Altera (a November 2015 white paper titled "Synchronous Ethernet Solutions with Altera FPGAs and Silicon Labs Jitter-Attenuating PLLs"). Petitioner also cited the Stratix Handbook and the Si5345 Manual as extrinsic evidence describing features necessarily present in the components disclosed by Altera.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Altera discloses a complete, high-performance Synchronous Ethernet (SyncE) solution that uses an Altera Stratix V FPGA interoperating with an external Silicon Labs Si5345 jitter-attenuating PLL. This combination allegedly discloses every limitation of the challenged claims. The system receives serial data, uses the external PLL to generate synchronized clocks for the FPGA's internal processing without clock domain crossing, processes the data within the FPGA, and transmits a new serial data stream. The Stratix Handbook and Si5345 Manual were used to demonstrate the inherent operation of the specific FPGA and PLL components referenced in Altera, such as the functions of the deserializer, serializer, and the phase detector within the PLL.
    • Key Aspects: The core of this ground rested on the argument that Altera’s explicit combination of a specific, commercially available FPGA and a specific external PLL for clock synchronization inherently performed the steps of the claimed method.

Ground 2: Claims 1, 2, 8, 10-11, and 19-20 are obvious over Altera in view of Lockwood under 35 U.S.C. §103.

  • Prior Art Relied Upon: Altera (the same 2015 white paper) and Lockwood (a 2012 paper titled "A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)").

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground asserted that even if the preamble of claim 1 is limiting, the combination of Altera and Lockwood renders it obvious. Altera taught the technical solution of using an FPGA with an external PLL to achieve low-latency clock synchronization for Ethernet networking. Lockwood taught the application of low-latency FPGA-based systems specifically for high-frequency trading (HFT). Lockwood described processing incoming "market data" feeds to generate outgoing "order entry data" or "trading data," directly corresponding to the data types recited in the preamble of claim 1 and in dependent claim 20.
    • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine Altera's low-latency clocking solution with Lockwood's HFT application to achieve a competitive advantage. Lockwood emphasized that minimizing latency is critical in HFT, and Altera’s system directly addressed latency by eliminating clock-domain crossing circuits. Because Lockwood identified Ethernet as prevalent in the HFT ecosystem, a POSITA would have looked to Altera’s high-performance Ethernet solution as a natural fit for the HFT systems Lockwood described.
    • Expectation of Success: A POSITA would have a high expectation of success because FPGAs are inherently programmable. The computational circuitry of the Altera FPGA could be readily configured to implement the trading algorithms and data processing logic for HFT applications as described by Lockwood.

  • Additional Grounds: Petitioner asserted an alternative obviousness challenge (Ground 1B) based on Altera, the Stratix Handbook, and the Si5345 Manual, arguing that if a POSITA did not understand the features of the Stratix FPGA and Si5345 PLL to be inherently present in Altera, it would have been obvious to combine the three references as Altera expressly directed users to such documentation.

4. Key Claim Construction Positions

  • For purposes of the IPR, Petitioner adopted constructions consistent with the patent specification and the Patent Owner's implicit constructions from related district court litigation.
  • "deserializer": Construed to include a receiver Physical Medium Attachment (PMA) and a receiver Physical Coding Sublayer (PCS), consistent with diagrams and descriptions in the ’286 patent.
  • "serializer": Construed to include a transmitter PCS, a transmitter PMA, a transmitter buffer, and clock generation blocks, also based on the patent’s specification.

5. Key Technical Contentions (Beyond Claim Construction)

  • Petitioner's primary technical contention was that it is proper to rely on extrinsic evidence (the Stratix Handbook and Si5345 Manual) to demonstrate the inherent features of components explicitly named in a primary prior art reference (Altera). Petitioner argued that a POSITA, upon reading Altera’s disclosure of a system using a Stratix V FPGA and a Si5345 PLL, would understand that the standard, documented features of those specific commercial products are necessarily present in the disclosed system.

6. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, stating that the co-pending district court litigation was in its infancy, with no trial date set and no discovery completed, resulting in negligible investment by the court and parties.
  • It was further argued that the primary prior art references, particularly the Altera white paper, were not before the examiner during prosecution. Petitioner contended that Altera was easily found via a simple internet search and its absence from the prosecution history underscores the petition's strong merits.

7. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 2, 8, 10-11, 19, and 20 of the ’286 patent as unpatentable.