Phison Electronics Corp v. Vervain LLC

1. Case Identification

• Case #: PGR2025-00010
• Patent #: 11,967,369
• Filed: December 26, 2024
• Petitioner(s): Phison Electronics Corporation
• Patent Owner(s): Vervain, LLC
• Challenged Claims: 1-10

2. Patent Overview

• Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
• Brief Description: The ’369 patent describes a non-volatile memory system that combines multi-level cell (MLC) and single-level cell (SLC) NAND flash memory. The system uses a controller to perform a "data integrity test" and remap data from MLC to SLC components upon test failure, purportedly to maximize the operational lifetime of the system.

3. Grounds for Unpatentability

Ground 1: Claims 1-10 are patent-ineligible under 35 U.S.C. §101 as directed to an abstract idea.

• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the claims are directed to the abstract idea of a "memory space," which is merely a property of memory (storage capacity) and not a concrete technological improvement. The petition asserted that the term "memory space" only appears in the specification to describe market share or relative storage capacity.
  • Motivation to Combine (for §103 grounds): Not applicable.
  • Key Aspects: Petitioner contended the additional claim limitations, such as a controller and memory elements, merely recite well-understood, conventional hardware performing routine functions. The claims allegedly fail to integrate the abstract idea into a practical application and lack an inventive concept, serving only to preempt the use of a known data management technique on a generic computer architecture. The further subdivision into "logical and physical" memory spaces was described as adding no technical substance.

Ground 2: Claims 1-10 are invalid under 35 U.S.C. §112(a) for lack of written description.

• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that key claim terms, including "memory space" and "memory element," lack antecedent basis in the specification. The specification allegedly describes a physical system of distinct MLC and SLC modules, while the claims abstract these components into unsupported "spaces" and "elements."
  • Motivation to Combine (for §103 grounds): Not applicable.
  • Key Aspects: The petition asserted that the claimed functional relationships—such as the controller being "operable" to retain data in Random Access Volatile Memory (RAVM) and the comparison of "stored data" to "retained data"—are not explained or enabled by the specification. This alleged lack of support for the claimed structure and operations demonstrates that the inventor did not possess the claimed invention.

Ground 3: Claims 1-10 are obvious under 35 U.S.C. §103 over Gavens in view of POSITA knowledge.

• Prior Art Relied Upon: Gavens (Patent 8,634,240) and its incorporated references, in view of the general knowledge of a Person of Ordinary Skill in the Art (POSITA).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued Gavens discloses a complete multi-modal NAND flash system with all the key features of claim 1. Gavens teaches a memory array partitioned into a high-density portion (native MLC) and a lower-density, higher-endurance portion (MLC operating in a pseudo-SLC, or "pSLC," mode). Gavens’s controller performs post-write-read error management by comparing data written to the MLC portion with a cached original copy (a data integrity test). If errors exceed a threshold (test failure), the original data is rewritten to the more robust pSLC portion (remapping).
  • Motivation to Combine (for §103 grounds): A POSITA would find it obvious to substitute a "native" SLC module for Gavens's pSLC portion to achieve even better performance and endurance, a simple and predictable design choice. The motivation was to use known techniques to enhance memory system lifetime, which is the explicit goal of both the ’369 patent and the prior art.
  • Expectation of Success: A POSITA would have a high expectation of success, as combining distinct SLC and MLC modules into a hybrid system was a known strategy for wear-leveling and error management.
  • Key Aspects: Dependent claims 2-10 were argued to be obvious as they add only conventional features, such as implementing a Flash Translation Layer (FTL) in software (claim 2), using flash memory (claim 4), employing standard DRAM or SRAM for the cache (claims 5-6), or remapping to the SLC portion upon failure (claim 9), all of which were disclosed in Gavens or were common knowledge.

• Additional Grounds: Petitioner asserted that claims 1-10 are invalid for indefiniteness under 35 U.S.C. §112(b). The arguments focused on the ambiguity of terms like "memory space" and "memory element," the functional and unsupported claiming of the "controller," and the indefinite nature of when the "data integrity test" must be performed.

4. Key Claim Construction Positions

• "MLC memory module" vs. "SLC memory module": Petitioner argued that based on the specification and POSITA understanding, these terms refer to physically distinct hardware modules with different underlying circuitry.
  • An "MLC memory module" was construed as comprising non-volatile memory cells arranged with circuitry capable of storing multiple logical pages in a single physical page of cells.
  • An "SLC memory module" was construed as comprising non-volatile memory cells with circuitry incapable of storing multiple logical pages in a single physical page. This distinction is critical to the obviousness argument, contrasting a physically distinct SLC module with the pSLC mode of an MLC module taught in Gavens.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under Fintiv. The petition asserted that the parallel district court proceeding was in its early stages, with no substantive opinions issued and fact discovery having just commenced. It was argued that a Board review would be more efficient than district court litigation, which involves eight related patents and complex claim construction issues, and that the compelling merits of the petition weigh strongly in favor of institution to promote patent quality.

6. Relief Requested

• Petitioner requests institution of post-grant review and cancellation of claims 1-10 of the ’369 patent as unpatentable.