PTAB

PGR2025-00071

Samsung Electronics Co Ltd v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Package with Stacked Array Dies
  • Brief Description: The ’087 patent relates to a dynamic random access memory (DRAM) package featuring stacked semiconductor dies. The technology purports to solve the problem of high electrical load on signal drivers by replacing a single driver with two or more drivers, each coupled to a distinct subset of the stacked memory dies, thereby reducing the load on each individual driver and improving performance.

3. Grounds for Unpatentability

Ground 1: Lack of Written Description - Claims 1-28 are invalid under 35 U.S.C. §112

  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the ’087 patent fails to provide adequate written description for the specific, lengthy, and complex combinations of limitations recited in each independent claim. The specification allegedly provides only a "laundry list" of disparate features and possibilities, with over 100 million potential combinations, without describing or disclosing the particular combinations that were ultimately claimed. This requires an impermissible "picking and choosing" of elements with the benefit of hindsight.
    • Key Aspects: Petitioner asserted that the specification lacks support for several key limitations. For example, it fails to disclose the claimed unidirectional interconnects configured to conduct signals down the stack (from DRAM dies to the control die), only disclosing unidirectional interconnects for signals up the stack. Furthermore, claims 24-28 were argued to be indefinite and lack written description because they recite contradictory and nonsensical requirements for "fifth," "sixth," and "eighth" signals, such as being associated with both read and write operations simultaneously.

Ground 2: Obviousness over Keeth and Shaeffer - Claims 1-28 are obvious over Keeth in view of Shaeffer

  • Prior Art Relied Upon: Keeth (Patent 9,123,552) and Shaeffer (Patent 9,665,507).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Keeth taught the foundational architecture of a stacked memory device, including multiple DRAM dies stacked on an interface die with interleaving conductive paths and independently controlled "vaults" to increase bandwidth. However, Keeth lacked detail on specific high-speed signaling protocols. Shaeffer allegedly supplied this missing element by teaching advanced signaling protocols for communication between a memory controller and memory devices, including the use of separate command/address (C/A) and data interconnects, and unidirectional strobe signals for read and write operations (e.g., TRS/EDC and data clocks).
    • Motivation to Combine: A POSITA would combine Shaeffer’s high-speed signaling protocols with Keeth’s stacked memory architecture to create a fully functional, high-performance device. Keeth provided a beneficial physical arrangement but was deficient in its disclosure of signaling details. A POSITA seeking to implement Keeth’s architecture would have looked to known, advantageous protocols like those in Shaeffer to increase data transfer bandwidth and enable reliable high-speed operation, which was a well-known goal in the art.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in this combination. Both references are from the same field of art (stacked memory devices), and integrating a known signaling protocol (Shaeffer) into a known physical memory stack (Keeth) was a predictable and well-understood engineering task.

Ground 3: Obviousness over Keeth, Shaeffer, and Riho2 - Claims 1-28 are obvious over Keeth and Shaeffer, further in view of Riho2

  • Prior Art Relied Upon: Keeth (Patent 9,123,552), Shaeffer (Patent 9,665,507), and Riho2 (Application # 2010/0195364).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon the combination of Keeth and Shaeffer by adding Riho2 to address limitations concerning driver size. Petitioner argued that the interleaving conductive paths in Keeth, which pass through different numbers of dies, would naturally have different lengths and therefore different parasitic capacitance and resistance. This creates a recognized problem of varying electrical loads. Riho2 directly addressed this issue by teaching the optimization of output driver capacity (i.e., driver size) to account for changes in the time constant caused by such parasitic effects in stacked chip assemblies. This maps directly to claim limitations requiring drivers of different sizes.
    • Motivation to Combine: A POSITA implementing the Keeth/Shaeffer combination would immediately recognize that the varying path lengths inherent in Keeth's architecture would lead to inconsistent signal timing and power integrity issues. Riho2 provided a known solution for this exact problem. Therefore, a POSITA would be motivated to incorporate Riho2’s technique of using different-sized drivers to stabilize high-frequency operations, improve signal integrity, and reduce power consumption across the varied interconnects of the Keeth stack.
    • Expectation of Success: Implementing Riho2’s driver-size optimization was well within the skill of a POSITA. The technique involved applying known circuit design principles to solve a predictable problem in the Keeth/Shaeffer architecture, and a POSITA would have a high expectation of success in achieving a more stable and efficient memory device.

4. Relief Requested

  • Petitioner requests institution of Post Grant Review and cancellation of claims 1-28 as unpatentable.