DCT
5:16-cv-00925
Papst Licensing GmbH & Co KG v. Xilinx Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Papst Licensing GMBH (Federal Republic of Germany)
- Defendant: Xilinx Inc (Delaware)
- Plaintiff’s Counsel: Farnan LLP; Dinovo Price Ellwanger & Hardy LLP
- Case Identification: 5:16-cv-00925, D. Del., 11/07/2014
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is incorporated in Delaware, has allegedly committed acts of infringement in the district, transacts business in the district, and/or has a regular and established place of business in the district.
- Core Dispute: Plaintiff alleges that Defendant’s field-programmable gate array (FPGA) design and simulation software infringes patents related to methods for verifying memory test protocols against operating constraints.
- Technical Context: The technology concerns software-based simulation methods for validating the correctness of test sequences for complex memory devices before running them on physical hardware.
- Key Procedural History: The complaint alleges that Plaintiff acquired the patents-in-suit from Rambus, Inc. It further alleges that Defendant had notice of the ’891 Patent as early as March 4, 2006, due to a USPTO Examiner’s search report during the prosecution of a Xilinx patent. Plaintiff also alleges it provided Defendant with notice of infringement for both patents on January 24, 2014, followed by a meeting between the parties on October 16, 2014.
Case Timeline
| Date | Event |
|---|---|
| 2000-01-18 | Priority Date for ’759 and ’891 Patents |
| 2003-06-03 | Issue Date for U.S. Patent No. 6,574,759 |
| 2004-03-09 | Issue Date for U.S. Patent No. 6,704,891 |
| 2006-03-04 | Alleged notice date to Xilinx of the ’891 Patent |
| 2014-01-24 | Plaintiff notice to Xilinx of alleged infringement |
| 2014-10-16 | Parties allegedly met to discuss infringement |
| 2014-11-07 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,574,759, “METHOD FOR VERIFYING AND IMPROVING RUN-TIME OF A MEMORY TEST,” issued June 3, 2003
The Invention Explained
- Problem Addressed: The patent’s background describes the increasing complexity of memory devices and the corresponding proliferation of operating constraints (e.g., timing rules) that must be obeyed during testing. This created a "chicken and egg" problem where it was difficult to determine if a test failure was caused by a faulty memory device or by an improperly constructed test that violated a constraint ('759 Patent, col. 2:28-38).
- The Patented Solution: The invention discloses a method to validate a memory test before it is used on physical hardware. It involves creating a time-ordered set of test operations and processing it through a software "simulator" that is programmed with the memory device's specific operating constraints. The simulator checks for violations and outputs error messages, allowing a test writer to debug and verify the test protocol in a virtual environment ('759 Patent, Abstract; col. 5:5-35; Fig. 2).
- Technical Importance: This method provided an automated and systematic approach to verify test protocol compliance, improving testing efficiency and preventing functional memory devices from being erroneously discarded due to invalid tests ('759 Patent, col. 3:15-29).
Key Claims at a Glance
- The complaint asserts infringement of one or more claims, including at least claim 4, which depends from independent claim 1 (Compl. ¶14).
- Independent Claim 1:
- developing a set of operations defining the test, where the set of operations is ordered in time;
- passing the set of operations through a simulator capable of determining whether the set of operations violates any one of the operating constraints; and
- upon determining that the set of operations violates any one of the operating constraints, outputting an error message, wherein the error message comprises an adjustment to the set of operations which will resolve the operating constraint violation.
- The complaint reserves the right to assert other claims, which may include dependent claims (Compl. ¶17).
U.S. Patent No. 6,704,891, “METHOD FOR VERIFYING AND IMPROVING RUN-TIME OF A MEMORY TEST,” issued March 9, 2004
The Invention Explained
- Problem Addressed: As a continuation of the application leading to the ’759 Patent, the ’891 Patent addresses the same technical challenge: the difficulty and uncertainty of generating valid test routines for modern, complex memory devices with numerous and strict operating rules ('891 Patent, col. 2:25-38).
- The Patented Solution: The patent describes a method of simulating a memory device's behavior by defining its operating constraints, providing a time-ordered set of operations, and using a simulator to determine if any operation violates a constraint. If a violation is found, the system outputs an error message ('891 Patent, Abstract; col. 5:6-37).
- Technical Importance: The solution enables pre-verification of memory tests, which helps ensure test accuracy and separates the process of test validation from the need for a "known-good" physical device, thereby streamlining the semiconductor testing workflow ('891 Patent, col. 3:15-29).
Key Claims at a Glance
- The complaint asserts infringement of one or more claims, including at least independent claim 1 (Compl. ¶20).
- Independent Claim 1:
- A method of simulating the behavior of a memory device, the method comprising:
- defining a set of operating constraints based on the characteristics of the memory device;
- providing a set of memory device operations, wherein the set of memory device operations is ordered in time;
- passing the set of operations through a simulator capable of determining whether the set of memory device operation violates any one of the operating constraints; and
- outputting an error message upon determining that the set of operations violates any one of the operating constraints.
- The complaint reserves the right to assert other claims (Compl. ¶23).
III. The Accused Instrumentality
- Product Identification: The accused instrumentalities are Xilinx’s Virtex-7 and Virtex-6 FPGAs when used with its design and simulation software, including the ISE Design Suite, Vivado Design Suite, ISE Simulator (ISim) tool, CORE Generator tool, and Memory Interface Generator (MIG) tool (Compl. ¶15, ¶21).
- Functionality and Market Context: The complaint alleges these products constitute "design software and tools that generate and verify tests for memory" (Compl. ¶14, ¶20). In combination, these tools allegedly allow users to configure memory controllers for Xilinx FPGAs, generate test sequences for those controllers, and simulate their operation to verify compliance with memory protocol rules. The complaint notes that Defendant provides this software to its customers via its support website (Compl. ¶12). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint does not contain a detailed claim chart. The following tables summarize the infringement theory inferred from the complaint's general allegations.
’759 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| developing a set of operations defining the test, where the set of operations is ordered in time | A user employs Xilinx's design tools (e.g., MIG tool) to generate a configuration and test bench for a memory interface, creating a time-ordered sequence of test operations. | ¶14, ¶15 | col. 9:20-24 |
| passing the set of operations through a simulator capable of determining whether the set of operations violates any one of the operating constraints | The generated test sequence is run through the Xilinx ISE Simulator (ISim) tool, which allegedly simulates the operations against a model of the memory device and its operating constraints. | ¶14, ¶15 | col. 9:25-29 |
| upon determining that the set of operations violates any one of the operating constraints, outputting an error message...comprises an adjustment...which will resolve the...violation | The ISim tool is alleged to output error messages when a memory constraint is violated, with the complaint asserting this functionality verifies the test. | ¶8, ¶14, ¶15 | col. 9:30-34 |
’891 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| defining a set of operating constraints based on the characteristics of the memory device | Xilinx’s tools (e.g., MIG) allow users to select memory types and parameters, which allegedly define the set of operating constraints for the subsequent simulation. | ¶20, ¶21 | col. 9:15-18 |
| providing a set of memory device operations, wherein the set of memory device operations is ordered in time | A user or the design tools generate a stimulus file or test bench containing a sequence of time-ordered operations to exercise the memory interface. | ¶20, ¶21 | col. 9:19-22 |
| passing the set of operations through a simulator capable of determining whether the set of memory device operation violates any one of the operating constraints | The Xilinx ISim tool simulates the test sequence against the defined memory model to check for violations of protocol and timing rules. | ¶20, ¶21 | col. 9:23-27 |
| outputting an error message upon determining that the set of operations violates any one of the operating constraints | The ISim tool allegedly generates an error or warning in a log file or console output when the simulation detects a violation of a memory constraint. | ¶8, ¶20, ¶21 | col. 9:28-31 |
- Identified Points of Contention:
- Technical Questions: The complaint does not provide specific evidence showing that Xilinx's general-purpose simulator performs the specialized functions described in the patents. A key question will be whether the ISim tool's error-checking capabilities are coextensive with the "set of operating constraints" for a given memory device, as contemplated by the claims.
- Scope Questions: For the ’759 Patent, a primary issue will be whether the "error message" from Xilinx's tools "comprises an adjustment...which will resolve the...violation." The complaint does not allege facts to support this specific element, raising the question of whether an error message that merely identifies a fault, without suggesting a solution, meets the claim limitation.
V. Key Claim Terms for Construction
The Term: "simulator" (’759 Claim 1; ’891 Claim 1)
- Context and Importance: The function of the "simulator" is the core of the claimed methods. The dispute may center on whether Defendant's ISim tool, a component of a larger design suite, qualifies as the claimed "simulator."
- Intrinsic Evidence for a Broader Interpretation: The claims themselves do not heavily qualify the term, referring simply to a "simulator capable of determining whether the set of operations violates" constraints. This may support an interpretation covering any software tool that models a system and checks rules.
- Intrinsic Evidence for a Narrower Interpretation: The specification describes the simulator in the specific context of memory device testing, noting that it receives a "parameter file...that describes the architectural and timing characteristics of the memory device" and models behavior on a "communications channel" ('759 Patent, col. 5:9-13). This context may support a construction limited to simulators specifically configured for or focused on memory protocol verification.
The Term: "error message comprises an adjustment" (’759 Patent, Claim 1)
- Context and Importance: This limitation is present in claim 1 of the ’759 Patent but not in claim 1 of the ’891 Patent, making its definition critical to distinguishing the scope of the two patents and analyzing infringement of the ’759 Patent. Practitioners may focus on this term because the complaint lacks specific factual allegations showing that Xilinx's tools provide such an "adjustment."
- Intrinsic Evidence for a Broader Interpretation: The specification states "error messages may offer suggested fixes, such as timing adjustments" ('759 Patent, col. 4:65-66). Plaintiff may argue that an error message providing sufficient diagnostic information for a user to calculate the required adjustment effectively "comprises" that adjustment.
- Intrinsic Evidence for a Narrower Interpretation: The claim language "comprises an adjustment...which will resolve" the violation suggests the error message must contain the solution itself, not merely data from which a solution can be derived. The use of "suggested fixes" in the specification could be argued to require an explicit recommendation, which Defendant may contend its tools do not provide.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement for both patents. It asserts that Xilinx provides the accused software and instructs customers on its infringing use through "tutorials, user guides, product guides, and other documentation" available on its website. Knowledge and specific intent are alleged based on pre-suit notice (Compl. ¶16, ¶22).
- Willful Infringement: The complaint does not use the word "willful," but it alleges facts that would support such a claim. It pleads that Xilinx had knowledge of the patents due to direct notice letters from Papst in 2014 and, for the ’891 Patent, from a USPTO action in 2006, and that Xilinx continued to infringe despite this knowledge (Compl. ¶9-12).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of "definitional scope and evidentiary proof," particularly for the ’759 Patent: can Plaintiff produce evidence that the "error message" generated by Xilinx’s simulation tools does more than merely flag a timing violation and instead provides or "comprises an adjustment" that resolves the violation, as strictly required by claim 1?
- A key evidentiary question will be one of "technical implementation:" beyond the general allegations in the complaint, does the accused Xilinx software suite, when used as instructed, actually perform the specific, holistic method of verifying a test against a complete set of memory "operating constraints," or is there a functional mismatch between the patent's specialized teaching and the operation of Defendant's general-purpose design tools?
- The case may also turn on a question of "infringing party:" the complaint accuses a "combination" of software tools used to "generate and verify tests" (Compl. ¶15, ¶21). This raises a central question of whether Papst can establish direct infringement by Xilinx itself, or if its case will depend on proving that Xilinx's customers are the direct infringers and that Xilinx is liable for inducing their conduct.