Oak IP LLC v. GlobalFoundries Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Oak IP, LLC (Texas)
  • Defendant: GlobalFoundries Inc. (Cayman Islands) and GlobalFoundries US., Inc. (Delaware)
  • Plaintiff’s Counsel: Bayard, P.A.; Nelson Bumgardner Conroy PC
• Case Identification: Civil Action No. [Not provided in complaint], D. Del., 02/04/2025
• Venue Allegations: Plaintiff alleges venue is proper for GlobalFoundries Inc. under the alien-venue rule as it is not a U.S. resident. Venue is alleged to be proper for GlobalFoundries US., Inc. because it is a Delaware corporation and therefore resides in the district.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor chips, manufactured using its 14nm and 12nm FinFET processes, infringe three patents related to methods for reducing electrical resistance at metal-semiconductor junctions.
• Technical Context: The technology concerns the fabrication of electrical junctions between metal contacts and semiconductor materials, a fundamental challenge in creating smaller, faster, and more efficient integrated circuits.
• Key Procedural History: The complaint does not mention any prior litigation or administrative proceedings. However, the provided patent documents for U.S. Patent Nos. 9,905,691 and 10,090,395 include Inter Partes Review (IPR) Certificates. For the ’691 Patent (IPR2020-01206), asserted claim 19 was found patentable, while other claims were cancelled. For the ’395 Patent (IPR2020-01207), asserted claim 17 was found patentable, while other claims were cancelled. These proceedings may influence claim construction by providing prosecution history that could be argued to limit the scope of the surviving claims.

Case Timeline

Date	Event
2012-07-18	Earliest Patent Priority Date ('691, '395, '880 Patents)
2016-06-29	Accused Product Launch (AMD Radeon RX 480)
2018-02-27	U.S. Patent No. 9,905,691 Issues
2018-10-02	U.S. Patent No. 10,090,395 Issues
2021-03-02	U.S. Patent No. 10,937,880 Issues
2025-02-04	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,905,691 - "Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions"

The Invention Explained

• Problem Addressed: The patent’s background explains that at a conventional junction between a metal and a semiconductor, the electrical properties are dominated by a "Schottky barrier" (Compl. ¶29). The height of this barrier is influenced by surface-level electronic phenomena like "metal induced gap states" (MIGS), which effectively "pin" the Fermi level and prevent engineers from creating devices with specifically desired electrical characteristics. This problem becomes more acute as device sizes shrink (Compl. ¶31; ’691 Patent, col. 3:4-10).
• The Patented Solution: The invention proposes inserting a very thin interface layer between the metal and the semiconductor. This layer is designed to be thick enough to physically separate the metal from the semiconductor to reduce the effects of MIGS, and to "passivate" the semiconductor surface by terminating chemically reactive "dangling bonds" (Compl. ¶36; ’691 Patent, col. 4:1-6). At the same time, the layer must be thin enough to allow electrons to pass through it via quantum tunneling, thereby maintaining a low-resistance electrical connection. The inventors theorized the existence of an ideal interface thickness that minimizes contact resistance by balancing these competing effects (Compl. ¶37, Fig. 7; ’691 Patent, Fig. 8).
• Technical Importance: This technique allows the barrier height to be "tuned" based on the bulk properties of the chosen metal rather than being dictated by surface states, enabling the creation of semiconductor devices with "designer characteristics" (Compl. ¶31; ’691 Patent, col. 3:7-10).

Key Claims at a Glance

• The complaint asserts at least independent claim 1 and dependent claim 19 (Compl. ¶49).
• Independent Claim 1 requires:
  • a semiconductor region in a substrate;
  • a metal electrical contact to said semiconductor region;
  • a passivating dielectric tunnel barrier layer between said semiconductor region and said metal electrical contact; and
  • the semiconductor region being electrically connected to the metal electrical contact through the layer.
• Dependent Claim 19 further requires the layer to comprise a metal oxide and a semiconductor oxide, the semiconductor region to comprise silicon, and the metal contact to comprise titanium.
• The complaint expressly reserves the right to assert additional claims (Compl. ¶49, fn. 18).

U.S. Patent No. 10,090,395 - "Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions"

The Invention Explained

• Problem Addressed: As with the ’691 Patent, this patent addresses the challenge of Fermi level pinning at metal-semiconductor junctions, which constrains the design of high-performance semiconductor devices (’395 Patent, col. 3:4-10). The patents share a nearly identical specification (Compl. ¶26, fn. 8).
• The Patented Solution: The solution is the introduction of a thin, engineered interface layer between the metal and semiconductor to decouple the junction’s electrical properties from surface-level effects, thereby enabling tunable barrier heights while maintaining low contact resistance (’395 Patent, col. 4:1-11, Fig. 8).
• Technical Importance: The invention provides a method to overcome fundamental limitations in semiconductor fabrication, allowing for the creation of devices with tailored electrical properties essential for continued miniaturization and performance improvements (’395 Patent, col. 3:7-10).

Key Claims at a Glance

• The complaint asserts at least independent claim 17 (Compl. ¶65).
• Independent Claim 17 requires:
  • a source or drain of a transistor, comprising a semiconductor;
  • a metal electrical contact to said source or drain; and
  • an interface layer disposed between and electrically connecting the source or drain and the metal contact, where the interface layer comprises an oxide of titanium and an oxide of the semiconductor.
• The complaint expressly reserves the right to assert additional claims (Compl. ¶49, fn. 18).

U.S. Patent No. 10,937,880 - "Method for Depinning the Fermi Level of a Semiconductor at an Electrical Junction and Devices Incorporating Such Junctions"

Multi-Patent Capsule

• Technology Synopsis: The patent discloses an electrical junction for a transistor that uses a multi-component interface layer to control the electrical barrier between a metal contact and a silicon-based source or drain. This interface layer includes a titanium oxide "spacer layer" and a very thin "semiconductor oxide passivation layer" (less than 1 nm) to achieve low-resistance contacts with desired electrical characteristics (’880 Patent, Abstract; Claim 1).
• Asserted Claims: Independent claim 1 (Compl. ¶75).
• Accused Features: The complaint alleges that chips manufactured by Defendant include an interface layer with a titanium silicon oxide spacer layer and a silicon oxide passivation layer less than 1 nm thick, located between the metal contact and the silicon source/drain (Compl. ¶¶76, 78-79).

III. The Accused Instrumentality

• Product Identification: The accused instrumentalities are semiconductor chips manufactured by GlobalFoundries using its 14nm and 12nm FinFET fabrication processes (Compl. ¶40). The complaint identifies downstream consumer products incorporating these chips, including the AMD Radeon RX 480, AMD Ryzen 5 2600, and AMD Ryzen 5 1600 AF processors (Compl. ¶41).
• Functionality and Market Context: The accused chips are fundamental components of modern processors used in a wide range of applications, including personal computers, data centers, and graphics technologies (Compl. ¶41). The complaint alleges that these chips incorporate the patented technology at the physical junction between metal contacts and the semiconductor source/drain regions. The infringement allegations are supported by microscopic images of a chip from an AMD Ryzen 5 1600 AF processor, which purport to show the material composition of these junctions (Compl. ¶¶50-52, Fig. 9). The complaint alleges these chips are manufactured at Defendant's Fab 8 facility in New York (Compl. ¶42).

IV. Analysis of Infringement Allegations

'691 Patent Infringement Allegations

Claim Element (from Independent Claim 1 & Dependent Claim 19)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a semiconductor region in a substrate... [which] comprises silicon	The accused chips comprise an n-doped silicon semiconductor region, identified as the maroon-colored area in a microscopic image.	¶50, ¶55	col. 2:19-20
a metal electrical contact to said semiconductor region... [which] comprises titanium	The accused chips comprise a tungsten and titanium nitride metal electrical contact, identified by orange, green, and blue colors in a microscopic image.	¶51, ¶58	col. 14:6-10
a passivating dielectric tunnel barrier layer between said semiconductor region and said metal electrical contact... [which] comprises a metal oxide and a semiconductor oxide	The accused chips comprise a layer of titanium silicon oxide and silicon oxide located between the silicon region and the metal contact, identified by purple and pink colors.	¶52, ¶54	col. 10:15-18
said semiconductor region being electrically connected to said metal electrical contact through said passivating dielectric tunnel barrier layer	The alleged layer is structured to allow the flow of electric current between the metal contact and the silicon region.	¶53	col. 8:1-4

'395 Patent Infringement Allegations

Claim Element (from Independent Claim 17)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a source or drain of a transistor, said source or drain comprising a semiconductor	The accused chips comprise a silicon semiconductor source or drain, identified as the maroon-colored area in a microscopic image.	¶66	col. 18:20-22
a metal electrical contact to said source or drain	The accused chips comprise a tungsten and titanium nitride metal electrical contact.	¶67	col. 13:35-41
an interface layer disposed between and in contact with said source or drain and said metal electrical contact... and said interface layer comprising an oxide of titanium and an oxide of the semiconductor	The accused chips comprise an interface layer of titanium silicon oxide and silicon oxide, identified by purple and pink colors in a microscopic image.	¶68	col. 18:46-52
said source or drain being electrically connected to said metal electrical contact through said interface layer	The interface layer allegedly connects the silicon source/drain and the metal contact to allow for the flow of an electrical current.	¶68	col. 18:46-52

Identified Points of Contention

• Scope Questions: A central question may be whether the term "passivating," as used in the patents, requires a specific, intentional process designed to terminate dangling bonds, or if it can read on any thin oxide layer that incidentally forms during fabrication and may partially reduce surface states. A defendant could argue that incidental layers are well-known in the art and do not perform the inventive "passivating" function. The complaint's infringement allegations are illustrated with a microscopic image from an AMD chip, described as showing an n-doped silicon region (Compl. ¶50, Fig. 9).
• Technical Questions: The complaint's primary evidence of the infringing structure consists of color-coded microscopic images (e.g., Compl. ¶¶50-52, Figs. 9-11). A key question will be what evidentiary support exists to prove that these different colored regions correspond to the specific chemical compositions required by the claims (e.g., "titanium silicon oxide," "an oxide of titanium"). The complaint alleges this "on information and belief," suggesting that discovery into the actual composition and properties of the accused layers will be critical. For the ’880 Patent, establishing that the "semiconductor oxide passivation layer" is in fact "less than about 1 nm" thick will be a key factual hurdle (Compl. ¶79).

V. Key Claim Terms for Construction

• The Term: "passivating dielectric tunnel barrier layer" (’691 Patent, Claim 1)

• Context and Importance: This term encapsulates the core of the invention. Its construction will be critical, as it defines both the structure and function of the claimed interface. The dispute will likely focus on what properties a layer must have to be considered "passivating" and a "tunnel barrier," and whether the accused layer in Defendant's chips meets that definition. Practitioners may focus on this term because the functionality it implies—actively reducing surface states to "depin" the Fermi level—is key to distinguishing the invention from prior art incidental oxide layers.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification defines "passivation" as "the elimination or at least the reduction of the effects of surface states" (’691 Patent, col. 9:36-39). This language could support an interpretation where even a partial reduction in surface states is sufficient to meet the limitation.
  • Evidence for a Narrower Interpretation: The specification repeatedly links the invention to a specific technical goal: achieving an optimal interface thickness that minimizes contact resistance by balancing MIGS reduction with tunneling current, as depicted in Figure 8 (’691 Patent, col. 14:44-59). A defendant may argue that the term should be limited to layers intentionally engineered to achieve this specific balance, not just any thin dielectric layer.

• The Term: "interface layer comprising an oxide of titanium and an oxide of the semiconductor" (’395 Patent, Claim 17)

• Context and Importance: This term defines the material composition of the claimed invention. Proving infringement requires showing the presence of these two specific oxide types in the accused products. The complaint alleges the layer is "titanium silicon oxide and silicon oxide" (Compl. ¶68). The defense may challenge whether this mixture constitutes the two distinct oxides required by the claim language.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent claims do not specify if the oxides must be in distinct sub-layers or can be a composite material like a silicate. The use of "comprising" suggests an open-ended list. A plaintiff may argue that a material like titanium silicon oxide inherently contains both an "oxide of titanium" and an "oxide of the semiconductor" (silicon).
  • Evidence for a Narrower Interpretation: The ’880 patent, from the same family, explicitly claims a "spacer layer that is an oxide of titanium and a semiconductor oxide passivation layer," which could suggest that the inventors viewed these as distinct components (’880 Patent, col. 18:48-50). A defendant could use this language from a related patent to argue that the terms in the ’395 patent should also be interpreted as requiring two structurally or chemically distinct oxide components, not a single composite material.

VI. Other Allegations

• Indirect Infringement: The complaint makes a passing allegation of infringement by "encourag[ing] others to use their products and services" (Compl. ¶2). However, the formal counts for infringement are limited to direct infringement under 35 U.S.C. § 271(a), and the complaint does not plead specific facts to support the knowledge and intent required for claims of induced or contributory infringement.
• Willful Infringement: The complaint does not contain allegations of pre-suit knowledge of the patents-in-suit or other facts that would typically support a claim for willful infringement. The prayer for relief includes a request for enhanced damages, but this is not accompanied by a formal count for willfulness in the body of the complaint (Compl. ¶84(v)).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be one of evidentiary proof: can the plaintiff, through discovery and expert analysis, prove that the layered structures within Defendant's mass-produced FinFET chips have the precise chemical compositions (e.g., "an oxide of titanium and an oxide of the semiconductor") and perform the specific quantum-level functions (e.g., "passivating" the surface to "depin" the Fermi level) required by the patent claims?

2. The case will likely turn on a question of definitional scope: does the term "passivating," in the context of the patents, require an intentionally engineered layer designed to achieve a specific reduction in contact resistance, or can it be construed more broadly to cover any thin, incidental oxide layer that may form during fabrication and inherently provides some reduction in surface states?

3. A key legal question will be the impact of prior administrative review: how will the prosecution history from the IPR proceedings, which resulted in the cancellation of numerous claims across the asserted patent families, be used to argue for a narrower construction of the surviving asserted claims and the key terms within them?