DCT

2:24-cv-01078

Advanced Memory Tech LLC v. SK Hynix Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-01078, E.D. Tex., 04/02/2025
  • Venue Allegations: Venue is alleged to be proper because the defendant is not a resident of the United States and may be sued in any judicial district. The complaint further alleges that the defendant has established minimum contacts with Texas through the sale, distribution, and support of its products within the state, both directly and through major customers with substantial operations in Texas, such as Dell Technologies, NVIDIA, and Microsoft.
  • Core Dispute: Plaintiff alleges that Defendant’s NAND flash and DRAM semiconductor memory modules infringe five U.S. patents related to the design and operation of booster circuits, internal voltage generators, and memory device structures.
  • Technical Context: The patents address fundamental circuit-level challenges in semiconductor memory, a critical component in virtually all modern electronic devices, to improve efficiency, reduce physical footprint, and enhance performance.
  • Key Procedural History: The complaint alleges that the defendant had pre-suit knowledge of U.S. Patent Nos. 7,777,557, 7,920,018, and 7,969,231 because they were identified as prior art during the prosecution of the defendant's own patent applications, a factor that may be relevant to the plaintiff's claims of willful infringement.

Case Timeline

Date Event
2007-01-17 Priority Date for U.S. Patent No. 7,777,557
2007-01-17 Priority Date for U.S. Patent No. 7,920,018
2008-07-09 Priority Date for U.S. Patent No. 7,969,231
2009-02-06 Priority Date for U.S. Patent No. 8,400,835
2010-03-10 Priority Date for U.S. Patent No. 8,593,888
2010-08-17 U.S. Patent No. 7,777,557 Issues
2011-04-05 U.S. Patent No. 7,920,018 Issues
2011-06-28 U.S. Patent No. 7,969,231 Issues
2013-03-19 U.S. Patent No. 8,400,835 Issues
2013-11-26 U.S. Patent No. 8,593,888 Issues
2016-06-17 Alleged SK hynix Knowledge of '231 Patent via Citation in Prosecution
2022-02-03 Alleged SK hynix Knowledge of '557 Patent via Citation in Prosecution
2022-02-03 Alleged SK hynix Knowledge of '018 Patent via Citation in Prosecution
2025-04-02 Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,777,557 - “Booster Circuit,” issued August 17, 2010

The Invention Explained

  • Problem Addressed: The patent describes a problem in conventional booster circuits (or "charge pumps") used in semiconductor devices. These circuits often use transistors with a "triple-well structure." In such designs, a parasitic capacitance forms between the N-well and the substrate, which is repeatedly charged and discharged during operation. This process consumes power and reduces the circuit's boost efficiency (’557 Patent, col. 2:8-28).
  • The Patented Solution: The invention proposes a booster circuit with two parallel rows of "boosting cells." An analog comparison circuit monitors the output potentials of corresponding cells in each row and uses this comparison to control the potential of the N-well. By fixing the N-well potential to the lower of the two output potentials, the invention aims to suppress the amplitude of N-well potential fluctuations, thereby reducing the charging and discharging of the parasitic capacitance and improving boost efficiency without significantly increasing the circuit's physical layout area (’557 Patent, Abstract; col. 2:49-62).
  • Technical Importance: This approach seeks to enhance power efficiency in on-chip voltage generation, a critical factor for low-power semiconductor devices such as flash memories (’557 Patent, col. 1:8-14).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 14 (Compl. ¶67).
  • Essential elements of independent claim 1 include:
    • A plurality of "boosting cells", each having a specified triple-well structure with a switching element.
    • A "first boosting cell row" and a "second boosting cell row" comprising these cells.
    • At least one "analog comparison circuit" that outputs a "well bias potential".
    • This well bias potential is generated based on an "output potential" from a cell in the first row and an "output potential" from a cell in the second row.
    • The generated well bias potential is applied to the first well region of the switching element in cells of both rows.

U.S. Patent No. 7,920,018 - “Booster Circuit,” issued April 5, 2011

The Invention Explained

  • Problem Addressed: As a divisional of the application that led to the ’557 Patent, the ’018 Patent addresses the same technical problem of reduced boost efficiency in charge pump circuits due to parasitic capacitance associated with triple-well structures (’018 Patent, col. 2:19-38).
  • The Patented Solution: The solution is structurally similar to that of the ’557 Patent, employing two rows of boosting cells and an analog comparison circuit to control the N-well potential. However, the claimed embodiment generates the controlling well bias potential based on the input potentials of the boosting cells rather than their output potentials (’018 Patent, col. 2:56-61; Claim 1). This provides an alternative method for stabilizing the N-well potential to improve efficiency.
  • Technical Importance: The invention offers a different circuit-level implementation to solve the same power efficiency problem in on-chip voltage boosters, which is significant for devices requiring multiple internal voltage levels (’018 Patent, col. 1:19-25).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶90).
  • Essential elements of independent claim 1 include:
    • A "first boosting cell row" and a "second boosting cell row".
    • At least one "analog comparison circuit" for outputting a "well bias potential".
    • This well bias potential is generated based on an "input potential" from a cell in the first row and an "input potential" from a cell in the second row.
    • A detailed recitation that "each boosting cell includes" the specified triple-well structure.
    • The generated well bias potential is applied to the first well region of the switching element in cells of both rows.

U.S. Patent No. 7,969,231 - “Internal Voltage Generating Circuit,” issued June 28, 2011

  • Technology Synopsis: This patent addresses the need for stable voltage generation after an initial startup period. The invention describes a circuit with two boost circuits, a frequency dividing circuit, and a buffer. After startup, the frequency of the clock signal supplied to the second boost circuit can be reduced, which can lower current consumption and reduce voltage fluctuations, leading to a more stable output voltage (’231 Patent, Abstract; col. 4:5-23).
  • Asserted Claims: Independent claims 1 and 3 (Compl. ¶113).
  • Accused Features: The complaint alleges that internal voltage generating circuits within both Accused Flash Memory Modules (e.g., SK hynix Gold P31 SSD) and Accused DRAM Modules (e.g., SK hynix MDHD5E2100E LPDDR5x die) infringe the ’231 Patent (Compl. ¶113).

U.S. Patent No. 8,593,888 - “Semiconductor Memory Device,” issued November 26, 2013

  • Technology Synopsis: The patent describes a circuit architecture intended to reduce the physical area of a semiconductor memory device. The invention uses a single regulator whose output is selectively routed through different switches to control either the drain voltage of a memory cell (via a voltage applying transistor) or the gate voltage of the memory cell itself. This dual-purpose use of one regulator, instead of two separate ones, aims to reduce the overall circuit footprint (’888 Patent, Abstract; col. 2:32-44).
  • Asserted Claims: Independent claim 1 (Compl. ¶139).
  • Accused Features: The complaint alleges that embedded NOR Flash memory modules contained within SK hynix's Accused DRAM Modules (e.g., MDHD5E2100E LPDDR5x and H5CNAG8NM DDR5 dies) practice the claimed invention (Compl. ¶¶139, 142).

U.S. Patent No. 8,400,835 - “Non-volatile Semiconductor Memory,” issued March 19, 2013

  • Technology Synopsis: This invention addresses variations in write speed that occur when writing to multiple memory cells simultaneously. It discloses a system with M data lines connected to a larger number of bit lines, where multiple switches are provided for each data line. Switch control circuits can individually modulate the level or duration of the drain voltage applied to each bit line, allowing for fine-tuned control to compensate for variations and ensure more uniform write performance across cells (’835 Patent, Abstract; col. 2:41-52).
  • Asserted Claims: Independent claim 1 (Compl. ¶160).
  • Accused Features: The complaint alleges that embedded NOR Flash memory modules within SK hynix's Accused DRAM Modules infringe by using a similar switching architecture to control simultaneous write operations (Compl. ¶¶160, 163-164).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies three categories of accused products: "Accused Flash Memory Modules," "Accused 96-Layer and 128-Layer Flash Memory Modules," and "Accused DRAM Modules" (Compl. ¶¶63-65). Specific exemplary products include the SK hynix Gold P31 SSD, the SK hynix Platinum P41 SSD, and various LPDDR5x and DDR5 memory dies (Compl. ¶¶67, 78, 113, 139).

Functionality and Market Context

  • The accused products are semiconductor memory devices, including NAND flash non-volatile memory and DRAM volatile memory (Compl. ¶61). These components are fundamental to a vast array of modern electronics, including smartphones, servers, computers, and gaming consoles (Compl. ¶62). The complaint alleges that these memory modules incorporate on-chip booster circuits (charge pumps) and other voltage generation and control circuitry to manage the various internal voltages required for memory operations like programming and erasing (Compl. ¶¶70, 76, 117). The complaint also asserts that Defendant is a major global manufacturer of these components and sells them to large technology companies like Dell, NVIDIA, Microsoft, and AMD, which incorporate them into end-user products (Compl. ¶¶19-27). To support its venue allegations, the complaint includes a screenshot of an SK hynix social media post from a technology forum in Arlington, Texas, showcasing its memory technology (Compl. p. 4).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,777,557 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
boosting cells each having a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element... The accused SK hynix Gold P31 SSD allegedly has a booster circuit with boosting cells that include a first N-type well region, a second P-type well region within it, and one or more switching elements. ¶71 col. 2:50-54
a first boosting cell row...and...a second boosting cell row... The booster circuit in the Gold P31 SSD is alleged to contain two rows of boosting cells. ¶73 col. 3:4-6
at least one analog comparison circuit for outputting a well bias potential generated by an output potential of the boosting cell on the i-th stage... of the first boosting cell row and an output potential of the boosting cell on the i-th stage... of the second boosting cell row The circuit allegedly contains at least one analog comparison circuit transistor that generates a well bias potential based on an output potential from a boosting cell in each of the two rows. ¶74 col. 3:7-14
wherein the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element... The generated well bias potential is allegedly applied to the first well region of the switching element in the boosting cells of the two rows. ¶74 col. 3:14-19

U.S. Patent No. 7,920,018 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a first boosting cell row...and...a second boosting cell row... The booster circuit on the SK hynix Gold P31 is alleged to be comprised of two rows of boosting cells. ¶94 col. 3:5-7
at least one analog comparison circuit for outputting a well bias potential generated by an input potential of the boosting cell on the i-th stage...and an input potential of the boosting cell on the i-th stage... The circuit is alleged to contain at least one analog comparison circuit that outputs a well bias potential generated by an input potential from a boosting cell in each of the two rows. ¶95 col. 3:7-13
each boosting cell includes a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element... Within the booster circuit, each boosting cell allegedly includes a first N-type well region on a substrate, a second P-type well region within it, and one or more switching elements. ¶96 col. 2:56-61
the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element... The well bias potential from the analog comparison circuit is allegedly applied to the first well region of the switching element in the boosting cells of the two rows. ¶98 col. 3:17-21
  • Identified Points of Contention:
    • Technical Questions: The complaint's infringement theory rests on assertions from "Circuit extraction and scanning electron microscopy" (Compl. ¶¶71, 96), but no schematics or technical reports are provided. A central factual question will be whether discovery produces evidence that the accused circuits actually operate as alleged and contain all the structural elements required by the claims.
    • Scope Questions: A primary point of legal and technical contention may arise from the complaint's allegation that the same product (SK hynix Gold P31 SSD) infringes both the ’557 Patent and the ’018 Patent. Claim 1 of the ’557 Patent requires the well bias to be generated from the "output potential" of the cells, while claim 1 of the ’018 Patent requires it to be generated from the "input potential". This raises the question of whether the accused circuit can simultaneously meet both limitations, or if these represent alternative and potentially conflicting infringement theories.

V. Key Claim Terms for Construction

  • The Term: "output potential" (from ’557 Patent, claim 1)

    • Context and Importance: This term is central to the mechanism of the invention in the ’557 Patent. The definition of "output potential" will determine the precise electrical node whose voltage is used by the analog comparison circuit to generate the N-well bias, which is the core of the claimed efficiency improvement. Practitioners may focus on this term because its construction, relative to the term "input potential" in the ’018 Patent, could be case-dispositive for one or both patents.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification does not provide an explicit definition, which may support an argument for giving the term its plain and ordinary meaning as understood by a person of ordinary skill in the art, potentially covering any potential at or near the output stage of a boosting cell.
      • Evidence for a Narrower Interpretation: The detailed description and figures consistently associate the comparison with the "I/O terminals" (e.g., 111, 114, 113, 116) of the boosting cells (’557 Patent, col. 7:22-26; FIG. 1). A party might argue that "output potential" should be construed as being limited to the potential at these specific terminals.

  • The Term: "input potential" (from ’018 Patent, claim 1)

    • Context and Importance: This term is the primary feature distinguishing claim 1 of the ’018 Patent from claim 1 of its parent ’557 Patent. Its construction is critical because the complaint accuses the same device of infringing both claims, making the distinction between "input" and "output" potential a likely focal point of the dispute.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: Similar to "output potential," the specification does not explicitly define "input potential," which could support a broader construction encompassing any potential on the input side of a boosting cell's charge transfer transistor.
      • Evidence for a Narrower Interpretation: A party could argue that "input potential" must refer to the voltage from the preceding stage, before the boosting capacitor, to give the term a distinct meaning from "output potential" in the related ’557 Patent. The patent states that the comparison circuit is for "comparing input potentials of the boosting cells" (’018 Patent, col. 4:18-20), suggesting the potential is measured at the input of the cell stage itself.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all five asserted patents. The inducement claims are based on allegations that SK hynix actively encourages its customers (e.g., Dell, NVIDIA) to incorporate the infringing memory modules into their end products by providing technical support, specifications, firmware updates, and tailoring the modules to customer needs (e.g., Compl. ¶¶79, 102).
  • Willful Infringement: The complaint alleges willful infringement for the ’557, ’018, and ’231 patents based on pre-suit knowledge. It is alleged that SK hynix had actual knowledge of these patents since at least February 3, 2022 (’557 and ’018) and June 17, 2016 (’231), because the patents were identified as prior art during the prosecution of SK hynix's own patent applications (Compl. ¶¶85, 108, 134). For all patents, willfulness is also alleged based on knowledge since the filing of the initial complaint in the case (Compl. ¶¶87, 110, 136, 157, 180).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of claim scope and factual differentiation: The complaint asserts that the same accused product infringes two patents distinguished primarily by whether a control voltage is generated from a cell’s “input potential” (’018 Patent) or its “output potential” (’557 Patent). A key question for the court will be how to construe these terms and whether the accused circuit’s actual operation falls within the scope of one, both, or neither of these claims.
  • A key evidentiary question will be one of technical substantiation: The infringement allegations for all five patents rely heavily on conclusory statements derived from "circuit extraction." The case will likely turn on whether discovery and expert analysis produce concrete evidence to support these claims and demonstrate that the complex, multi-element structures recited in patents covering semiconductor memory architecture are, in fact, present in the accused products.
  • A critical question for damages will be one of subjective intent: The complaint alleges that SK hynix was aware of three of the asserted patents years before the lawsuit because they were cited during its own patent prosecution. This raises a significant question for the fact-finder: does this evidence of pre-suit knowledge rise to the level of "egregious" conduct necessary to support a finding of willful infringement and a potential award of enhanced damages?