2:25-cv-00324
Advanced Integrated Circuit Process LLC v. Taiwan Semiconductor Mfg Co Ltd
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Advanced Integrated Circuit Process LLC (Texas)
- Defendant: Taiwan Semiconductor Manufacturing Company Limited (Taiwan)
- Plaintiff’s Counsel: Susman Godfrey LLP; Miller Fair Henry PLLC
- Case Identification: 2:25-cv-00324, E.D. Tex., 04/01/2025
- Venue Allegations: Venue is alleged to be proper because the Defendant is not a resident of the United States and may therefore be sued in any judicial district. The complaint further details Defendant's extensive business contacts within Texas, including through subsidiaries, customer collaborations, and marketing events.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor manufacturing processes and the resulting integrated circuits, particularly those utilizing FinFET technology, infringe four U.S. patents related to semiconductor fabrication methods and device structures.
- Technical Context: The technology at issue involves advanced semiconductor manufacturing techniques used to create highly integrated circuits for high-performance computing, smartphones, and other consumer electronics.
- Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of three of the four asserted patents (’751, ’623, and ’572) based on those patents or their applications being cited as prior art during the prosecution of Defendant's own U.S. patent applications, which may support the allegations of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2003-09-26 | U.S. Patent No. 8,329,572 Priority Date |
| 2003-12-03 | U.S. Patent No. 7,439,623 Priority Date |
| 2003-12-03 | U.S. Patent No. 7,632,751 Priority Date |
| 2008-10-21 | U.S. Patent No. 7,439,623 Issues |
| 2009-11-03 | Alleged date of knowledge for '751 Patent by Defendant |
| 2009-12-15 | U.S. Patent No. 7,632,751 Issues |
| 2010-12-22 | Alleged date of knowledge for '623 Patent by Defendant |
| 2011-03-25 | U.S. Patent No. 8,884,373 Priority Date |
| 2012-12-11 | U.S. Patent No. 8,329,572 Issues |
| 2014-11-11 | U.S. Patent No. 8,884,373 Issues |
| 2018-02-06 | Alleged date of knowledge for '572 Patent by Defendant |
| 2024-10-01 | Start of high-volume production at Arizona fab (Q4 '24) |
| 2025-04-01 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,632,751 - “Semiconductor Device Having Via Connecting Between Interconnects,” issued December 15, 2009
The Invention Explained
- Problem Addressed: In advanced semiconductor manufacturing using copper interconnects, holding the device at high temperatures can cause vacancies (missing atoms) in the copper to migrate from larger interconnect structures into the smaller vertical connections, or "vias." This accumulation of vacancies can form a void, breaking the electrical connection and causing device failure (’623 Patent, col. 2:19-35).
- The Patented Solution: The patent describes a method for fabricating a "dummy via" near the functional via. This dummy via is not part of an active electrical circuit but is designed to act as a preferential sink for the migrating vacancies. By drawing vacancies away from the functional via, it reduces the stress gradient and suppresses the formation of voids, thereby improving the device's long-term reliability (’623 Patent, col. 2:54-65; FIG. 2A).
- Technical Importance: This method provides a structural solution to improve the reliability of multilevel copper interconnects, a critical factor for performance and longevity in densely packed, high-performance semiconductor devices (Compl. ¶74).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶63).
- Claim 1 recites a method for fabricating a semiconductor device with the essential steps of:
- forming a first interconnect on a semiconductor substrate;
- forming a first insulating film on the first interconnect;
- forming in the insulating film: a via hole connected to the first interconnect, a dummy hole "arranged so as to be incapable of having current flow therethrough," and an interconnect trench connected to both holes;
- depositing a conductive material into the holes and trench to form a via, a dummy via, and a second interconnect.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
U.S. Patent No. 7,439,623 - “Semiconductor Device Having Via Connecting Between Interconnects,” issued October 21, 2008
The Invention Explained
- Problem Addressed: The patent addresses the same technical problem as the ’751 Patent: the creation of voids in copper vias due to vacancy migration at high temperatures, which can lead to device malfunction (’623 Patent, col. 2:19-35).
- The Patented Solution: Rather than claiming the method of fabrication, this patent claims the resulting physical structure. The claimed semiconductor device includes a lower and upper interconnect, a functional via connecting them, and a "dummy via" also connected to the upper interconnect but arranged to be incapable of current flow. This structure, as illustrated in FIG. 2B, mitigates vacancy accumulation in the functional via (’623 Patent, col. 2:54-65).
- Technical Importance: The invention provides a specific device architecture aimed at enhancing the reliability of copper interconnects, which is essential as semiconductor feature sizes continue to shrink (Compl. ¶87).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶79).
- Claim 1 recites a semiconductor device with the essential components of:
- a semiconductor substrate, a first interconnect, a first insulating film, and a second interconnect;
- a via connecting the first and second interconnects;
- a dummy via connected to the second interconnect, "wherein the dummy via is made of a conductive film and is arranged so as to be incapable of having current flow therethrough";
- the second interconnect and the via form a dual damascene structure;
- the second interconnect and the dummy via also form a dual damascene structure.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
U.S. Patent No. 8,329,572 - “Semiconductor Device and Method for Fabricating the Same,” issued December 11, 2012
Technology Synopsis
This patent describes a method for protecting copper interconnect layers during fabrication. The method involves forming an "oxidation-resistant conductor film" (a cap layer, such as cobalt) over the copper interconnect before subsequent etching steps. This cap protects the underlying copper from damage or corrosion during the removal of other layers (Compl. ¶99).
Asserted Claims
Independent claim 1 is asserted (Compl. ¶97).
Accused Features
The complaint accuses TSMC's 3-, 4-, and 5-nanometer FinFET processes, which allegedly employ a "cobalt capping and photoresist mask method." Exemplary products cited include the Apple A15 Bionic and A18 Bionic chips (Compl. ¶¶96, 103).
U.S. Patent No. 8,884,373 - “Semiconductor Device,” issued November 11, 2014
Technology Synopsis
This patent claims a specific semiconductor device structure related to dual-gate electrodes used in complementary metal-oxide-semiconductor (CMOS) designs. The invention defines a structure with multiple gate electrodes formed from silicon films of different conductivity types (e.g., p-type for PMOS, n-type for NMOS), where the impurity concentration of a silicon film in one dual-gate electrode is higher than that in another, separate dual-gate electrode. This structure allows for precise control of transistor properties across different regions of a chip (Compl. ¶¶113-114, 116).
Asserted Claims
Independent claim 1 is asserted (Compl. ¶110).
Accused Features
The complaint accuses products manufactured using TSMC's 28-nanometer process node, specifically the Qualcomm MSM8960 semiconductor device (Compl. ¶¶108-109).
III. The Accused Instrumentality
Product Identification
The complaint identifies several groups of accused products based on the TSMC manufacturing process node used:
- "Accused FinFET Products" (for the ’751 and ’623 Patents) are semiconductor devices manufactured at TSMC's 3-, 4-, 5-, 6-, 7-, 10-, 12-, and 16-nanometer FinFET process nodes, with exemplars being the Broadcom BCM6715 and Qualcomm WCN7851 (Compl. ¶¶53-55).
- "Accused 3-, 4-, and 5-Nanometer Products" (for the ’572 Patent) include the Apple A18 Bionic and A15 Bionic chips (Compl. ¶¶56, 57, 58).
- "Accused 28-Nanometer Products" (for the ’373 Patent) include the Qualcomm Snapdragon S4 Plus MSM8960 (Compl. ¶¶59, 61).
Functionality and Market Context
The accused instrumentalities are advanced semiconductor devices that form the core processing components of modern electronics, including smartphones and networking equipment (Compl. ¶¶11, 52). The complaint alleges that the patented methods and structures are necessary features of TSMC's manufacturing processes at these advanced nodes, used for purposes such as ensuring consistent spacing between features like transistor fins, which becomes increasingly important at smaller scales (Compl. ¶74). The complaint presents promotional material for a TSMC symposium that lists its "advanced technology progress on 5nm, 4nm, 2nm processes" as a topic for customers (Compl. ¶25, p. 8). The complaint also points to TSMC's recruitment efforts in Texas, as shown in a LinkedIn post announcing campus visits to recruit for technical roles (Compl. ¶26, p. 9).
IV. Analysis of Infringement Allegations
7,632,751 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) forming a first interconnect on a semiconductor substrate | The method for fabricating the BCM6715 includes forming a first interconnect with a polysilicon layer on a semiconductor substrate. | ¶66 | '623 Pat, col. 9:1-3 |
| (b) forming a first insulating film on the first interconnect | A first insulating film, made of SiO2, is formed on the first interconnect. | ¶66 | '623 Pat, col. 9:3-5 |
| (c) forming in the first insulating film, a via hole connected to the first interconnect, a dummy hole which is arranged so as to be incapable of having current flow therethrough... | The method includes forming a via hole connected to the polysilicon first interconnect and also forming dummy holes connected to a floating dummy interconnect. | ¶¶67-68 | '623 Pat, col. 9:6-14 |
| ...and an interconnect trench connected to the via hole and the dummy hole | The method includes forming an interconnect trench in the first insulating film that is connected to both the via hole and the dummy hole. | ¶69 | '623 Pat, col. 9:9-12 |
| (d) depositing a conductive material in the via hole, the dummy hole and the interconnect trench, thereby forming a via, a dummy via and a second interconnect | The method includes depositing copper into the holes and trench, thereby forming a functional via, a dummy via, and a second interconnect. | ¶70 | '623 Pat, col. 9:14-19 |
7,439,623 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor device comprising: a semiconductor substrate; a first interconnect formed on the semiconductor substrate; a first insulating film formed on the first interconnect... | The WCN7851 comprises a semiconductor substrate, a first copper interconnect, and a first insulating film of silicon dioxide and silicon nitride. | ¶83 | col. 30:57-61 |
| a second interconnect formed on the first insulating film; a via formed through the first insulating film and connecting between the first and second interconnects... | The WCN7851 includes a second copper interconnect and a copper via connecting the first and second interconnects. | ¶83 | col. 31:1-5 |
| a dummy via connected to the second interconnect, wherein the dummy via is made of a conductive film and is arranged so as to be incapable of having current flow therethrough | The device includes a copper dummy via connected to the second copper interconnect and positioned so that current cannot flow through it. | ¶¶83-84 | col. 31:6-9 |
| the second interconnect and the via form a dual damascene structure, and the second interconnect and the dummy via form a dual damascene structure | In the WCN7851, the second interconnect and the via form a dual damascene structure, and the second interconnect and the dummy via also form a dual damascene structure. | ¶85 | col. 31:10-13 |
Identified Points of Contention
- Scope & Purpose Questions: For both the ’751 and ’623 patents, a central issue may be whether the accused "dummy" structures meet the claimed functional limitations. The complaint suggests these structures are created to "ensure consistent spacing between fins" (Compl. ¶74), a process-related purpose. This raises the question of whether a structure created for manufacturing uniformity can be considered the same as the claimed "dummy via," which the patents describe as a feature designed to solve the specific reliability problem of vacancy migration.
- Technical Questions: The infringement analysis for the ’623 Patent will depend on evidence that the accused WCN7851 device contains both a via and a dummy via that each form a "dual damascene structure" with the second interconnect. The complaint asserts this claim element is met (Compl. ¶85), but the technical basis for this conclusion will likely be a point of dispute.
V. Key Claim Terms for Construction
The Term
"dummy hole" (’751 Patent, Claim 1) / "dummy via" (’623 Patent, Claim 1)
Context and Importance
This term is the central inventive concept of both lead patents. The infringement case for these patents depends on whether the accused features—which the complaint alleges are used for process control and spacing (Compl. ¶74)—fall within the scope of this term. Practitioners may focus on this term because its construction will determine whether a feature created for manufacturing process uniformity can infringe a claim for a structure designed for long-term reliability.
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation: The patents define a dummy via functionally as one "which do not constitute a closed circuit in actual use" and is "incapable of having current flow therethrough" (’623 Patent, col. 3:14-19; Claim 1). Plaintiff may argue that any non-functional, conductive structure meeting these basic criteria and located near a functional via falls within the claim's scope, regardless of the manufacturer's primary reason for creating it.
- Evidence for a Narrower Interpretation: The "Summary of the Invention" repeatedly frames the dummy via's purpose as reducing the "stress gradient" and suppressing the "flowing of vacancies" to prevent voids (’623 Patent, col. 2:54-65). Defendant may argue that the term should be limited to structures intentionally designed and placed to solve this specific vacancy migration problem, not incidental features created for other manufacturing reasons like lithographic consistency.
VI. Other Allegations
Indirect Infringement
The complaint alleges inducement for all four patents based on Defendant actively encouraging customers like Apple, Broadcom, and Qualcomm to use its infringing manufacturing processes by promoting their technical and economic benefits (Compl. ¶¶75, 88, 104, 118). Contributory infringement is alleged for the ’623 and ’373 patents (the structure patents) on the basis that the accused semiconductor devices are a material part of the invention, are not staple articles of commerce, and are manufactured by Defendant for its customers (Compl. ¶¶91, 121).
Willful Infringement
Willfulness allegations for the ’751, ’623, and ’572 patents are based on alleged pre-suit knowledge. The complaint asserts Defendant was aware of these patents because their underlying applications were cited by the USPTO during the prosecution of Defendant’s own patent applications (Compl. ¶¶76, 93, 105). For the ’373 patent, the allegation is based on knowledge as of the filing of the complaint (Compl. ¶123).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope and inventive purpose: Can the term "dummy via," described in the '751 and '623 patents as a solution to the reliability problem of vacancy migration, be construed to cover semiconductor features that Defendant allegedly creates to ensure process uniformity and consistent spacing? The case may turn on whether the purpose for which a structure is created is relevant to the infringement analysis of the claims.
- A key evidentiary question will be one of proving the process: For the method claims of the ’751 and ’572 patents, Plaintiff must demonstrate that Defendant's confidential manufacturing processes perform the specific, ordered steps recited in the claims. This raises the question of what evidence, likely from extensive discovery or complex reverse engineering, will be required to prove that TSMC’s fabrication method for an Apple A18 Bionic chip, for example, meets every limitation of the claimed cobalt capping process.
- The dispute will likely involve a question of material science and claim construction: For the '373 patent, the infringement allegation relies on a specific "impurity concentration" being "higher" in one silicon film than in another. The case will raise questions of how this relative term is to be construed and what quantum of evidence from materials analysis of an accused chip is sufficient to prove this electrical property exists as claimed.