DCT

1:25-cv-01036

Advanced Memory Tech LLC v. Micron Technology Inc

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01036, W.D. Tex., 11/04/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains regular and established places of business in the district, including its Micron Storage Solutions Center in Austin, and commits acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s DRAM and NAND flash memory modules infringe five U.S. patents related to semiconductor circuit designs for on-chip voltage generation and management.
  • Technical Context: The technology at issue involves fundamental circuits, such as booster circuits and voltage regulators, used to manage electrical power within semiconductor memory chips, which are critical for device performance, power efficiency, and physical size.
  • Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of U.S. Patent Nos. 7,920,018 and 7,777,557 since at least September 30, 2011. This allegation is based on a patent application assigned to Defendant that cited the application corresponding to the ’557 Patent as prior art during its prosecution. This alleged pre-suit knowledge forms the basis for Plaintiff's willful infringement claims for these two patents.

Case Timeline

Date Event
2007-01-17 Priority Date for U.S. Patent Nos. 7,777,557 & 7,920,018
2008-07-09 Priority Date for U.S. Patent No. 7,969,231
2009-12-03 Priority Date for U.S. Patent No. 8,519,778
2010-03-04 Prosecution Event: Micron allegedly cites '557 application as prior art
2010-03-10 Priority Date for U.S. Patent No. 8,593,888
2010-08-17 Issue Date for U.S. Patent No. 7,777,557
2011-04-05 Issue Date for U.S. Patent No. 7,920,018
2011-06-28 Issue Date for U.S. Patent No. 7,969,231
2011-09-30 Alleged Date of Actual Knowledge for '018 and '557 Patents
2013-08-27 Issue Date for U.S. Patent No. 8,519,778
2013-11-26 Issue Date for U.S. Patent No. 8,593,888
2016-04-12 Micron announces opening of its Austin "MSSC" facility
2025-06-30 Initial Complaint Filing Date
2025-11-04 First Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,920,018 - “Booster Circuit,” issued Apr. 5, 2011

The Invention Explained

  • Problem Addressed: The patent's background describes an issue in conventional on-chip booster circuits that use triple-well transistors. To function efficiently, the potential of a specific layer (the N-well) must be controlled, but prior methods of doing so resulted in parasitic capacitance that consumed power, reduced boost efficiency, and required larger layout areas on the semiconductor die (U.S. Patent No. 7,920,018, col. 1:17-29).
  • The Patented Solution: The invention proposes a booster circuit architecture arranged in two parallel rows of "boosting cells." It introduces an "analog comparison circuit" that monitors the voltage potentials of corresponding cells in each row and selects either the higher or lower potential. This selected potential is then used to apply a bias to the N-well of other cells in the circuit. By decoupling the N-well control from the cell's primary charge path, this design claims to reduce the power lost to parasitic capacitance, improve overall boost efficiency, and allow for a more compact layout (’018 Patent, Abstract; col. 2:48-67).
  • Technical Importance: This circuit design aims to enhance the performance and reduce the physical size of on-chip voltage generators, which are fundamental components for enabling operations in memory devices like NAND flash (’018 Patent, col. 1:8-14).

Key Claims at a Glance

  • The complaint asserts at least independent Claim 1 (Compl. ¶41).
  • The essential elements of Claim 1 include:
    • A first and a second row of boosting cells.
    • At least one "analog comparison circuit" that outputs a "well bias potential" generated from the "input potential" of cells in each row.
    • Each boosting cell having a specific triple-well structure with a switching element.
    • The "well bias potential" from the comparison circuit being applied to the "first well region" of the switching element in at least one boosting cell.

U.S. Patent No. 7,969,231 - “Internal Voltage Generating Circuit,” issued Jun. 28, 2011

The Invention Explained

  • Problem Addressed: The patent addresses challenges in systems that use a primary boost circuit to power a secondary, higher-voltage boost circuit. Starting up the secondary circuit can be slow, and simply increasing its capacitor size to speed it up is inefficient and can destabilize the primary circuit's voltage output (U.S. Patent No. 7,969,231, col. 4:4-14).
  • The Patented Solution: The invention describes a two-stage voltage generation system where the clock signal supplied to the second charge pump is actively managed. It uses a frequency dividing circuit and a buffer circuit to supply a high-frequency clock to the second pump during startup for rapid activation. After startup is complete, the buffer circuit selects a lower, divided-frequency clock for the second pump. This approach claims to achieve a fast startup while ensuring stable, efficient operation thereafter (’231 Patent, Abstract; col. 4:36-53).
  • Technical Importance: This method provides a way to quickly enable multiple voltage domains within a semiconductor device without compromising power stability or efficiency, a common requirement in complex integrated circuits (’231 Patent, col. 1:19-24).

Key Claims at a Glance

  • The complaint asserts at least independent Claims 3 and 6 (Compl. ¶63).
  • The essential elements of Claim 3 include:
    • A first charge pump circuit generating a second voltage from a first voltage.
    • A second charge pump circuit generating a third voltage from the second voltage.
    • A "frequency dividing circuit" to create a second clock signal from a first clock signal.
    • A "buffer circuit" configured to "select" either the first or second clock signal and supply it to the second charge pump.
  • Claim 6 is broader, reciting a first and second charge pump where the frequency of the clock supplied to the second pump is "changed" to a frequency "obtained by dividing an original frequency".

Multi-Patent Capsule: U.S. Patent No. 8,519,778

  • Patent Identification: U.S. Patent No. 8,519,778, "Semiconductor Integrated Circuit and Booster Circuit Including the Same," issued Aug. 27, 2013 (Compl. ¶24).
  • Technology Synopsis: This patent discloses a circuit design intended to reduce high-frequency noise generated by the driver circuits of booster pumps. The solution involves placing a current source in series with the inverters that control the main transistors of the driver, where the current source's output is independent of the main supply voltage; this is alleged to slow down the transistor switching speed, thereby reducing noise (’778 Patent, Abstract; col. 2:19-35).
  • Asserted Claims: At least Claim 1 (Compl. ¶85).
  • Accused Features: The complaint alleges that Accused DRAM Modules, including the Micron DDR5 Y52K DRAM devices, contain the patented semiconductor integrated circuit (Compl. ¶85).

Multi-Patent Capsule: U.S. Patent No. 8,593,888

  • Patent Identification: U.S. Patent No. 8,593,888, "Semiconductor Memory Device," issued Nov. 26, 2013 (Compl. ¶28).
  • Technology Synopsis: This patent addresses the need for two separate regulators (one for the memory cell's drain voltage, one for its gate voltage) in certain memory operations. The invention claims a circuit that allows a single regulator to perform both functions by using a set of switches to route the regulator's output to control either a "voltage applying transistor" (for the drain) or the memory cell's gate directly, depending on the operation mode, thereby reducing circuit area (’888 Patent, Abstract; col. 1:33-45).
  • Asserted Claims: At least Claim 1 (Compl. ¶102).
  • Accused Features: The complaint alleges that Accused DRAM Modules, specifically the Micron DDR5 DRAM Y52K devices, utilize the patented memory device structure (Compl. ¶102).

Multi-Patent Capsule: U.S. Patent No. 7,777,557

  • Patent Identification: U.S. Patent No. 7,777,557, "Booster Circuit," issued Aug. 17, 2010 (Compl. ¶32).
  • Technology Synopsis: This patent is related to the ’018 Patent and describes a similar solution to the same technical problem. It discloses a booster circuit with two rows of cells and an analog comparison circuit that compares cell potentials to generate a well bias potential. This potential is then applied to the N-wells of switching elements to suppress substrate biasing effects, improve efficiency, and enable a more compact circuit layout (’557 Patent, Abstract; col. 2:30-43).
  • Asserted Claims: At least Claim 1 (Compl. ¶122).
  • Accused Features: The complaint alleges that Accused DRAM Modules, including the Micron DRAM LPDDR5X Y52P die and DDR5 DRAM Y32A die, incorporate the patented booster circuit (Compl. ¶122).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies two main categories of accused products: "Accused Flash Memory Modules" and "Accused DRAM Modules" (Compl. ¶¶ 38, 39).
    • Exemplar DRAM products include the Micron DRAM LPDDR5X Y52P die, DDR5 DRAM Y32A die, DDR5 Y52K die, LPDDR4 DRAM Z11M die, and LPDDR5 DRAM Y42M die (Compl. ¶¶ 41, 63, 85, 102, 122).
    • An exemplar Flash Memory product is the Micron B47R NAND Flash die (Compl. ¶63).
  • Functionality and Market Context: The accused products are semiconductor memory dies, including both volatile (DRAM) and non-volatile (NAND flash) memory types (Compl. ¶36). The complaint alleges that these memory modules are fundamental components manufactured by Micron and incorporated by its customers into a wide array of electronic products, including smartphones, servers, and computers (Compl. ¶37). The complaint asserts these products contain the specific booster circuits, voltage generating circuits, and memory device structures claimed by the patents-in-suit (e.g., Compl. ¶¶ 44, 66, 88). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,920,018 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a booster circuit comprising: a first boosting cell row ... a second boosting cell row ... The accused DRAM products contain a booster circuit comprised of two rows of boosting cells. ¶¶ 44, 45 col. 4:50-53
at least one analog comparison circuit for outputting a well bias potential generated by an input potential of the boosting cell on the i-th stage ... of the first boosting cell row and an input potential ... of the second boosting cell row ... The booster circuit includes at least one analog comparison circuit that outputs a well bias potential generated by an input potential of a boosting cell in each of the two rows. ¶46 col. 4:54-61
each boosting cell includes a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element... Each boosting cell in the accused products includes a first well region, a second well region within the first, and one or more switching elements. ¶47 col. 5:1-7
the at least one switching element is configured to transfer charges from a first terminal to a second terminal... The switching elements in the accused products transfer charges from one terminal to another. ¶48 col. 3:1-4
the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element included in the at least one boosting cell of the first and second boosting cell rows. The well bias potential from the analog comparison circuit is applied to the first well region of the switching element in the boosting cells of the two rows. ¶49 col. 5:12-17
  • Identified Points of Contention: The infringement allegations are conclusory and directly mirror the claim language without providing specific technical evidence.
    • Scope Questions: A central question may be whether the term "input potential" as used in the patent, which serves as the input to the comparison circuit, reads on the specific electrical nodes used for control in the accused products' booster circuits.
    • Technical Questions: A primary evidentiary question for the court will be whether the accused DRAM dies contain a circuit that performs the function of an "analog comparison circuit" as claimed. What evidence does the complaint provide that the accused products' voltage control scheme involves comparing potentials between two distinct rows of cells to generate a well bias, as opposed to a different known method of voltage regulation?

U.S. Patent No. 7,969,231 Infringement Allegations

Claim Element (from Independent Claim 3) Alleged Infringing Functionality Complaint Citation Patent Citation
An internal voltage generating circuit comprising: a first charge pump circuit ... and a second charge pump circuit ... The accused products contain an internal voltage generating circuit with a first charge pump generating a second voltage and a second charge pump generating a third voltage from the second. ¶¶ 67, 71, 72 col. 10:19-24
a frequency dividing circuit configured to divide a first clock signal to generate a second clock signal... The circuit includes a frequency dividing circuit that divides an initial clock signal to generate a second clock signal. ¶67 col. 10:25-27
a buffer circuit configured to select the first clock signal or the second clock signal and generate a third clock signal... The circuit includes a buffer circuit that generates a third clock signal from the first or second clock signal. ¶67 col. 10:28-31
wherein the third clock signal is supplied to the second charge pump circuit. The third clock signal from the buffer circuit is supplied to the second charge pump circuit. ¶68 col. 10:32-34
  • Identified Points of Contention: As with the ’018 patent, the allegations lack technical detail.
    • Scope Questions: For the broader Claim 6, a key issue may be the scope of "frequency ... is changed." Does this limitation require a switch between two distinct, continuous clock frequencies, or could it be construed to cover other clock management techniques like clock gating (starting/stopping the clock) or duty cycle modulation?
    • Technical Questions: What evidence does the complaint provide that the accused devices utilize a "buffer circuit configured to select" between two different clock sources as required by Claim 3? The analysis will likely focus on whether the accused clock management architecture matches the specific two-input, one-output selective structure claimed, or if it achieves a similar outcome through a non-infringing design.

V. Key Claim Terms for Construction

U.S. Patent No. 7,920,018

  • The Term: "analog comparison circuit"
  • Context and Importance: This term describes the core novel component of the invention. The outcome of the infringement analysis for the ’018 and ’557 patents will likely depend heavily on how this term is construed and whether Defendant’s products contain a structure that meets the resulting definition.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent functionally describes the circuit as one "for outputting the higher or lower of an input potential" from two different cells (’018 Patent, col. 4:54-61). This language could support a construction covering any circuit that performs this voltage selection function, regardless of its specific electronic implementation.
    • Evidence for a Narrower Interpretation: The figures and detailed description illustrate a specific embodiment using a pair of transistors (e.g., N-channel transistors 120, 121 in Fig. 1) with gates connected to the potentials to be compared (’018 Patent, Fig. 1). This could support a narrower construction limited to this differential-pair-like topology.

U.S. Patent No. 7,969,231

  • The Term: "buffer circuit configured to select"
  • Context and Importance: This term from Claim 3 recites the active mechanism for switching clock frequencies supplied to the second charge pump. Practitioners may focus on this term because it distinguishes the specific architecture of Claim 3 from other, potentially non-infringing methods of clock management.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim uses functional language. A party could argue that any circuit block that performs the function of selecting one of two input clock signals and outputting it meets this limitation, such as a standard multiplexer (MUX).
    • Evidence for a Narrower Interpretation: The embodiment shown in Figure 3 depicts a specific combination of logic gates (107-111) that not only selects the clock but also generates a complementary clock signal (’231 Patent, Fig. 3). A party may argue the term should be construed to require a structure consistent with this disclosed embodiment.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all five patents. Inducement allegations are based on Micron allegedly encouraging its customers to incorporate the accused modules into end products through marketing, sales, and technical support (e.g., Compl. ¶¶ 52, 75). Contributory infringement is alleged on the basis that the accused modules are a material part of the patented inventions, are not staple articles of commerce suitable for substantial non-infringing use, and are sold by Micron with knowledge of infringement (e.g., Compl. ¶¶ 57, 81).
  • Willful Infringement: Willfulness allegations for the ’018 and ’557 patents are based on alleged pre-suit actual knowledge since September 2011, stemming from a patent prosecution where an application assigned to Micron cited the ’557 patent's application as prior art (Compl. ¶¶ 58, 138). For the ’231, ’778, and ’888 patents, the willfulness allegations are based on knowledge allegedly acquired no later than the filing of the initial complaint in the case on June 30, 2025 (e.g., Compl. ¶¶ 82, 99).

VII. Analyst’s Conclusion: Key Questions for the Case

The complaint outlines a broad infringement action against core memory products. The case will likely turn on the following central questions:

  1. A core issue will be one of evidentiary proof: The complaint makes conclusory allegations that directly track the patent claims without providing technical schematics, reverse engineering analysis, or other factual support. A key question for the court will be whether Plaintiff can produce sufficient evidence to demonstrate that the complex, proprietary circuits within Micron's memory dies in fact practice the specific architectures required by the claims.

  2. A second central issue will be one of definitional scope and functional equivalence: The patents claim specific circuit arrangements, such as an "analog comparison circuit" and a "buffer circuit configured to select." A critical legal and technical question will be whether these terms can be construed to cover the actual circuits implemented by Micron, or if Micron’s designs, while achieving similar goals of voltage management and efficiency, do so through fundamentally different and non-infringing technical means.

  3. Finally, for the willfulness claims on the ’018 and ’557 patents, a key question will be one of corporate knowledge and intent: Can a citation to a patent application as prior art in the prosecution history of one of Defendant’s patents be sufficient to establish that the corporation had actual knowledge of the asserted patents and their specific technical teachings, thereby supporting a claim for willful infringement?