DCT

6:20-cv-00178

Godo Kaisha IP Bridge I v. Micron Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:20-cv-00178, W.D. Tex., 03/08/2021
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendants have committed acts of infringement in the district and maintain regular and established places of business there, including offices in Austin, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s DRAM, graphics memory, and other memory chips infringe four patents related to semiconductor device structures and manufacturing methods.
  • Technical Context: The technology at issue involves advanced fabrication techniques and structural designs for semiconductor memory devices, which are fundamental components for data storage in a vast range of electronic products.
  • Key Procedural History: The complaint states that Plaintiff contacted Defendant by letter on January 27, 2020, informing Defendant of its patent portfolio and its potential relevance to Defendant's DRAM business.

Case Timeline

Date Event
1999-10-26 U.S. Patent No. 6,445,047 Priority Date
2000-08-18 U.S. Patent No. 6,424,041 Priority Date
2001-02-09 U.S. Patent No. 7,189,616 Priority Date
2002-07-23 U.S. Patent No. 6,424,041 Issued
2002-09-03 U.S. Patent No. 6,445,047 Issued
2002-08-07 U.S. Patent No. 6,747,320 Priority Date
2004-06-08 U.S. Patent No. 6,747,320 Issued
2007-03-13 U.S. Patent No. 7,189,616 Issued
2020-01-27 Plaintiff IP Bridge sends notice letter to Defendant Micron
2020-02-05 Defendant Micron responds to Plaintiff's letter
2021-03-08 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,189,616 - "Semiconductor Memory Device with Trench-Type Stacked Cell Capacitors and Method for Manufacturing the Same"

The Invention Explained

  • Problem Addressed: The patent describes that as semiconductor devices shrink, the close proximity of trench-type stacked cell capacitors in a DRAM creates unwanted "parasitic capacitance" between them, which can interfere with the stored charge and lead to data errors or device malfunction (’616 Patent, col. 3:1-29).
  • The Patented Solution: The invention claims a method of manufacturing where the mask pattern used to create holes for capacitors is arranged in a "stagger manner." This layout ensures that the side edges of adjacent capacitors are only partially opposite each other, which reduces the area of interaction and thereby lowers the parasitic capacitance (’616 Patent, Abstract; col. 4:30-41).
  • Technical Importance: This manufacturing method allows for continued miniaturization and increased density of memory cells while maintaining the signal integrity required for reliable operation (Compl. ¶28).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶46).
  • The essential elements of claim 1, a method claim, include:
    • depositing an interlayer insulating film on a semiconductor substrate provided with contact plugs;
    • patterning a mask pattern on the interlayer insulating film, the mask pattern having a layout in which a plurality of hole patterns having the same shape are arranged in a stagger manner so that side edges of the adjacent hole patterns are only partially opposite to each other;
    • forming holes for storage nodes in the interlayer insulating film by etching with the mask pattern;
    • forming the storage nodes in the holes so as to be connected electrically to the contact plugs;
    • forming a capacitor insulating film on the storage nodes;
    • forming a plate electrode on the capacitor insulating film; and
    • wherein the length of a portion where the opposing capacitors are overlapped in the mask layout is set so that the value of the parasitic capacitance between adjacent cell capacitors is not more than 10% of the set cell capacitance value.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 6,747,320 - "Semiconductor Device with DRAM Inside"

The Invention Explained

  • Problem Addressed: The patent addresses performance issues in conventional CMOS sense amplifiers used in DRAMs. Imbalances between transistor pairs, caused by factors like parasitic capacitance or mask alignment shifts during fabrication, can degrade the sensitivity of the sense amplifier, making it difficult to reliably detect the small voltage differences stored in memory cells (’320 Patent, col. 1:53-67).
  • The Patented Solution: The patent claims a specific physical layout for a sense amplifier where pairs of gate electrodes for both N-type and P-type transistors are arranged in parallel to each other within a single active region, oriented in the same direction as the bit lines. Adjacent transistors are isolated using shallow trench isolation (STI), creating a symmetric structure that suppresses variations in transistor characteristics and enhances sensitivity (’320 Patent, Abstract; col. 2:20-33).
  • Technical Importance: This layout improves the speed and reliability of sense amplifiers, which is a critical factor for the performance of high-density DRAM co-resident with high-speed logic (Compl. ¶30).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶65).
  • The essential elements of claim 1, a device claim, include:
    • A semiconductor device comprising a DRAM region and a high-speed CMOS logic region that are co-resident with each other,
    • wherein a pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor constituting a CMOS sense amplifier of the DRAM are disposed respectively in one active region in parallel to each other in the same direction as that of bit lines, and
    • a pair of adjacent N-type sense amplifier transistors and a pair of adjacent P-type sense amplifier transistors are isolated by shallow trench isolation (STI) regions.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 6,445,047 - "Semiconductor Device and Method for Fabricating the Same"

  • Technology Synopsis: The patent addresses the challenge of creating MOSFETs with different threshold voltages on the same chip without degrading performance. It discloses a device with two types of MOSFETs: a first with a polysilicon gate electrode and a second with a refractory metal film gate electrode, which allows the second MOSFET to achieve a higher threshold voltage without requiring the increased dopant concentrations that can shorten data retention times and decrease carrier mobility (Compl. ¶32; ’047 Patent, col. 1:49–col. 2:6).
  • Asserted Claims: Dependent claims 2 and 4, based on independent claim 1 (Compl. ¶77).
  • Accused Features: The complaint alleges that the "LV peripheral transistors" in the accused chips correspond to the first claimed MOSFET, while the "recessed channel access transistors" with their TiN gates correspond to the second claimed MOSFET with a refractory metal gate (Compl. ¶¶82-86).

U.S. Patent No. 6,424,041 - "Semiconductor Device"

  • Technology Synopsis: The patent addresses the problem of copper atoms from copper wiring diffusing into adjacent silicon structures, which can cause short circuits and device malfunctions. The invention is a device structure that incorporates a "copper-diffusion blocking means" in a region surrounding the memory storage portion to physically prevent copper from the wiring portion from migrating into the sensitive memory area (Compl. ¶34; ’041 Patent, col. 1:35-41, Abstract).
  • Asserted Claims: Independent claim 1 (Compl. ¶95).
  • Accused Features: The complaint alleges that the accused chips include a memory portion (DRAM capacitors), a wiring portion with copper wire, and a "copper-diffusion blocking means," identified as a tungsten cell plate, which surrounds the memory portion (Compl. ¶¶101-103).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the accused products as "Accused Memory Chips," which include but are not limited to "GDDR5X, GDDR6, GDDR6X, and DDR5 memory chips" (Compl. ¶38). The infringement allegations focus on an exemplary technical analysis of a Micron MT58K256M32JA-100 GDDR5X SDRAM product (Compl. ¶38).

Functionality and Market Context

  • The Accused Memory Chips are described as high-performance memory components used in a wide range of markets, including cloud servers, enterprise computing, graphics processing, and mobile devices (Compl. ¶37). The complaint alleges these chips are essential components of the end-products into which they are integrated and that their manufacture and sale contribute significantly to Defendant's revenue (Compl. ¶¶39, 42). The technical allegations are supported by references to a "TechInsights Report," which appears to be a third-party reverse engineering analysis of the accused GDDR5X product (Compl. ¶38). Figure 3.1.7 is a transmission electron microscope (TEM) image showing a top-down view of the DRAM array at the capacitor storage node level, illustrating the dense, repeating layout of the memory cells (Compl. p. 17).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,189,616 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for manufacturing a semiconductor memory device comprising: depositing an interlayer insulating film on a semiconductor substrate provided with contact plugs; The Accused Memory Chips are allegedly formed by depositing an interlayer insulating film (e.g., SiN regions) on a substrate with contact plugs. ¶¶52, 53 col. 7:25-28
patterning a mask pattern on the interlayer insulating film, the mask pattern having a layout in which a plurality of hole patterns... are arranged in a stagger manner so that side edges of the adjacent hole patterns are only partially opposite to each other; The accused GDDR5X is allegedly formed using a mask pattern where the hole patterns for capacitors are arranged in a stagger manner. Figure 3.1.7 in the complaint is provided as visual evidence of this staggered layout. ¶54 col. 4:30-35
forming holes for storage nodes in the interlayer insulating film by etching with the mask pattern; The accused GDDR5X is allegedly formed by etching holes for storage nodes into the insulating film using the mask pattern. ¶55 col. 12:15-18
forming the storage nodes in the holes so as to be connected electrically to the contact plugs; The accused GDDR5X allegedly has storage nodes formed in the etched holes that are electrically connected to contact plugs. ¶56 col. 12:20-25
wherein the length of a portion where the opposing capacitors are overlapped in the mask layout is set so that the value of the parasitic capacitance between adjacent cell capacitors is not more than 10% of the set cell capacitance value. The complaint alleges that in the accused GDDR5X, the layout is set so the parasitic capacitance between adjacent DRAM cells is not more than 10% of the cell capacitance value. ¶59 col. 8:57-62
  • Identified Points of Contention:
    • Scope Questions: A central dispute may revolve around the term "stagger manner." The infringement question will depend on whether the accused product's specific capacitor layout falls within the scope of the claim's definition, which requires that "side edges of the adjacent hole patterns are only partially opposite to each other."
    • Technical Questions: The final "wherein" clause presents a quantitative limitation regarding parasitic capacitance ("not more than 10% of the set cell capacitance value"). The complaint asserts this limitation is met but does not provide calculations or data, instead referencing images of the "DRAM cells" (Compl. ¶59). A key technical question for the court will be what evidence proves this ratio. This suggests that discovery into Defendant's design parameters and extensive electrical modeling or testing may be required to resolve this factual dispute.

U.S. Patent No. 6,747,320 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A semiconductor device comprising a DRAM region and a high-speed CMOS logic region that are co-resident with each other, The accused GDDR5X is identified as a semiconductor integrated circuit device containing co-resident DRAM and high-speed CMOS logic regions. Figure 1.2.2 is a die photograph presented as evidence. ¶69 col. 2:23-25
wherein a pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor... are disposed respectively in one active region in parallel to each other in the same direction as that of bit lines, The Accused Memory Chips allegedly include N-type and P-type sense amplifier transistors whose gate electrodes are arranged in parallel to each other and to the bit lines. Figure 3.2.2 is provided as visual evidence of this alignment. ¶¶70, 71 col. 2:25-30
and a pair of adjacent N-type sense amplifier transistors and a pair of adjacent P-type sense amplifier transistors are isolated by shallow trench isolation (STI) regions. The Accused Memory Chips allegedly use shallow trench isolation (STI) regions to isolate adjacent sense amplifier transistors. ¶72 col. 2:30-33
  • Identified Points of Contention:
    • Scope Questions: The interpretation of the term "in one active region" may be a point of contention. The question for the court will be whether this requires both N-type and P-type transistor pairs to be formed within a single, contiguous, undifferentiated active area, or if it can read on standard CMOS layouts where N-type and P-type devices reside in separate but adjacent doped wells (e.g., an N-well within a P-substrate).
    • Technical Questions: The infringement allegation hinges on the specific topology of the sense amplifier. A technical question will be whether the accused device's layout is functionally and structurally the same as the claimed parallel arrangement, as opposed to alternative, known sense amplifier layouts like the conventional ring-type structure the patent sought to improve upon (’320 Patent, FIG. 5).

V. Key Claim Terms for Construction

  • Term: "stagger manner" (’616 Patent, Claim 1)

  • Context and Importance: This term defines the core geometric layout of the capacitors, which is the basis of the invention's solution to reduce parasitic capacitance. Its construction will be determinative of infringement for the ’616 patent.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party could argue that the plain language, "so that side edges of the adjacent hole patterns are only partially opposite to each other," is a broad functional definition that covers any layout that is not perfectly aligned and achieves this partial opposition.
    • Evidence for a Narrower Interpretation: A party could point to the specific arrangement depicted in the patent's figures (e.g., ’616 Patent, FIG. 1) as the definitive example, arguing that "stagger manner" requires a specific alternating offset pattern, potentially limiting the claim's scope to layouts closely resembling the embodiment.

  • Term: "parasitic capacitance between adjacent cell capacitors is not more than 10% of the set cell capacitance value" (’616 Patent, Claim 1)

  • Context and Importance: This is a quantitative functional limitation that sets a specific performance threshold. Proving whether the accused method results in a product meeting this ratio is essential for infringement. Practitioners may focus on this term because such ratio-based limitations often lead to complex evidentiary disputes over testing methodologies and measurement conditions.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party may argue that the terms should be given their plain and ordinary meaning as understood in the art, referring to standard methods for calculating or measuring cell and parasitic capacitance under normal operating conditions.
    • Evidence for a Narrower Interpretation: A party could argue that the specification provides a specific context for how these values should be understood. For example, the patent calculates a parasitic capacitance of 5.3% for a conventional layout under a specific set of dimensional and material assumptions (’616 Patent, col. 8:26-34). A dispute may arise over whether the "10%" threshold must be evaluated using the same or similar contextual assumptions.

  • Term: "in one active region" (’320 Patent, Claim 1)

  • Context and Importance: This term specifies the physical location of the sense amplifier's N-type and P-type transistor pairs. Its construction will determine whether a standard CMOS architecture, which typically uses separate N-wells and P-wells, can infringe.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification discusses placing transistors on a "P-type semiconductor substrate" and an "N-type semiconductor substrate" in the context of N-type and P-type transistor pairs, respectively (’320 Patent, FIG. 5 background art description; col. 2:25-33). A party could argue "one active region" refers to the overall functional area of the sense amplifier, not a single, uniformly doped silicon region.
    • Evidence for a Narrower Interpretation: The claim language recites "in one active region," which could be interpreted narrowly to mean a single, contiguous, and undivided area of the substrate. A party might argue this was intended to distinguish the invention from prior art that might have used more physically separated transistor layouts.

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement, stating that Defendant actively and knowingly encourages its customers, OEMs, and others to make, use, sell, and import the infringing Accused Memory Chips (Compl. ¶¶47, 66, 78, 96). It also alleges contributory infringement on the basis that the Accused Memory Chips are a material component of the patented inventions, are especially made or adapted for an infringing use, and are not a staple article of commerce (Compl. ¶¶48, 67, 79, 97).
  • Willful Infringement: The complaint does not use the term "willful infringement." However, it alleges facts that may support such a claim by asserting that Defendant gained knowledge of its infringement at least as of the filing of the action and, for post-suit conduct, acts "knowingly, and intentionally" (Compl. ¶¶47, 66, 78, 96). Furthermore, the complaint alleges that Plaintiff provided pre-suit notice to Defendant via a letter dated January 27, 2020, which may be used to argue knowledge prior to the lawsuit's filing (Compl. ¶43).

VII. Analyst’s Conclusion: Key Questions for the Case

This case presents a technically detailed dispute over the micro-architecture and fabrication methods of modern DRAM chips. The resolution will likely depend on the court’s determination of the following central questions:

  • A core issue will be one of structural correspondence and claim scope: Do the specific layouts within the accused Micron memory chips—such as the "staggered" capacitor arrangement ('616 patent), the parallel sense amplifier transistor layout ('320 patent), the use of refractory metal gates ('047 patent), and the tungsten cell plate ('041 patent)—fall within the boundaries of the patent claims as they would be construed by the court?
  • A second key issue will be one of evidentiary proof for functional claims: The complaint relies on structural analysis from a reverse engineering report to allege infringement of claims that contain functional or quantitative limitations (e.g., the "10% parasitic capacitance" rule of the '616 patent). A key question for the litigation will be whether this structural evidence is sufficient to prove these functional requirements are met, or if more extensive discovery into Defendant's manufacturing processes and direct electrical testing of the accused chips will be necessary.