SanDisk Corp v. Netlist Inc

1. Case Identification

• Case #: IPR2015-01021
• Patent #: 8,081,536
• Filed: April 7, 2015
• Petitioner(s): SanDisk Corporation
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1, 16, 17, 24, 30, 31

2. Patent Overview

• Title: Memory Module with a Circuit for Improving Performance
• Brief Description: The ’536 patent describes a memory module and a circuit for increasing memory capacity and performance. The circuit allows a module with a larger number of lower-density memory devices (e.g., four ranks) to be recognized and used by a computer system as if it were a module with a smaller number of higher-density memory devices (e.g., two ranks) by generating additional chip select signals. The patent also discloses selectively isolating the electrical load of memory ranks from the computer system.

3. Grounds for Unpatentability

Ground 1: Obviousness over Takeda and Karabatsos - Claims 1 and 24 are obvious over Takeda in view of Karabatsos.

• Prior Art Relied Upon: Takeda (Japanese Patent Application Publication No. H10-320770), Karabatsos (Patent 6,446,158).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Takeda disclosed the core concept of the independent claims: a memory module that simulates a specific configuration to a computer system. Takeda’s module had more memory banks (ranks) than the computer system expected and included a bank control unit that received a smaller number of chip-select signals and generated a larger number of internal chip-select signals to control the additional ranks. Petitioner asserted that Takeda failed to explicitly teach using phase-locked clock signals or selectively isolating memory loads. Karabatsos allegedly supplied these missing elements, teaching the use of a Phase-Locked Loop (PLL) to generate clock signals for high-speed operation and the use of FET switches to electrically isolate deselected memory chips, thereby reducing capacitive load and power consumption.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Karabatsos’s known techniques with Takeda’s memory module design to achieve predictable benefits. Applying a PLL as taught by Karabatsos would improve timing control, and implementing its isolation switches would yield the well-understood results of reduced capacitive load and lower power consumption in Takeda's module.
  • Expectation of Success: A POSITA would have a high expectation of success, as incorporating standard components like PLLs and isolation switches into a memory module architecture was a common and well-understood engineering practice.

Ground 2: Obviousness over Takeda, Karabatsos, and JEDEC - Claims 16, 17, 30, and 31 are obvious over Takeda, Karabatsos, and JEDEC.

• Prior Art Relied Upon: Takeda, Karabatsos, and JEDEC (JEDEC Standard 21-C: DDR SDRAM Registered DIMM Design Specification, Jan. 2002).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination in Ground 1 to address the limitations of the dependent claims, which required storing data accessible to the computer system that characterizes the memory module as having attributes different from its actual physical attributes. Petitioner contended that the JEDEC standard supplied this teaching by describing a Serial Presence Detect (SPD) device, a standard component on memory modules used to store their operational parameters ("attributes"). In the context of Takeda’s rank-simulating module, a POSITA would store the emulated attributes (e.g., two ranks) in the SPD, not the actual attributes (e.g., four ranks). This would ensure the computer system’s memory controller interfaced correctly with the module, thereby meeting the claim limitation of storing data reflecting attributes different from the module's actual physical configuration. JEDEC also specified that such attributes include the number of row/column addresses and physical banks.
  • Motivation to Combine: A POSITA would be motivated to consult JEDEC because Takeda explicitly stated that JEDEC documents are used to describe memory module configurations. JEDEC provided the necessary, standard implementation details, such as the use of an SPD, for the type of module disclosed in Takeda.

Ground 3: Obviousness over Amidi and Connolly - Claims 1, 16, 17, 24, 30, and 31 are obvious over Amidi in view of Connolly.

• Prior Art Relied Upon: Amidi (Application # 2006/0117152), Connolly (Patent 6,070,217).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner presented Amidi as a stronger primary reference that disclosed a four-rank DDR memory module designed to emulate a two-rank module. Amidi's circuit received two input chip-select signals and generated four output chip-select signals. Critically, Amidi also explicitly disclosed a PLL for generating phase-locked clock signals and an SPD for storing module attributes, thus teaching most of the claimed features. However, Amidi did not explicitly disclose selectively isolating the load of the memory circuits. Petitioner argued that Connolly supplied this missing element by teaching the use of switches on a memory module to isolate memory chips from the data bus to reduce capacitive loading.
  • Motivation to Combine: A POSITA would combine Connolly’s load isolation technique with Amidi’s module to solve the known problem of high capacitive load on the memory bus. This combination would predictably reduce load and power consumption in Amidi’s design, a common goal in memory system engineering.
  • Expectation of Success: Integrating a known switching technique for load reduction from Connolly into the memory module design of Amidi would be a straightforward application of a known solution to a known problem with predictable results.
• Additional Grounds: Petitioner asserted an additional obviousness challenge against all claims based on the combination of Takeda, JEDEC, and Connolly, which relied on similar theories but used Connolly instead of Karabatsos to teach selective load isolation.

4. Key Claim Construction Positions

• "Rank": Petitioner argued that in the context of the ’536 patent, a "rank" is "a block or area that is created using some or all of the memory chips on a memory module." This construction was asserted to be consistent with the specification and necessary to interpret Takeda's disclosure of memory "banks" as corresponding to the claimed "ranks."

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 16, 17, 24, 30, and 31 of the ’536 patent as unpatentable.