PTAB

IPR2018-00063

Nanya Technology Corp v. Lone Star Silicon Innovations LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Transistor with a Trenched Gate and Method of Manufacture
  • Brief Description: The ’061 patent relates to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device and its manufacturing method. The key feature is a gate electrode buried inside a trench etched into a silicon substrate, a design intended to improve packing density, scalability, and manufacturability compared to conventional planar gate structures.

3. Grounds for Unpatentability

Ground 1: Claims 1, 3-4, 11, 13-14 are anticipated by Anderson

  • Prior Art Relied Upon: Anderson (Patent 5,300,447).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Anderson, which teaches a recessed channel MOS transistor to reduce punchthrough sensitivity, disclosed every limitation of the challenged claims. Petitioner asserted that Anderson’s MOS device was formed in a p-type semiconductor substrate (10) with doped source/drain regions (12). Anderson explicitly taught etching a "trench, or groove" (4) into the substrate between the source and drain regions. For the critical "trench-to-gate insulating layer," Petitioner contended that Anderson’s process—which forms nitride sidewalls (16a) on the trench walls and a gate oxide layer (17a) on the trench bottom—results in a single contiguous insulating layer. Finally, Anderson’s deposition of a polysilicon gate conductor (18) into the insulated trench was mapped to the claimed "trenched gate electrode." Dependent claims were allegedly met by specific conductivity types and the separate formation steps for the sidewall and bottom dielectric layers in Anderson.

Ground 2: Claims 1, 3, 11, and 13 are anticipated by Tanaka

  • Prior Art Relied Upon: Tanaka (Patent 5,408,116).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Tanaka, which discloses a "grooved-gate" MOS transistor to suppress punchthrough effects in miniaturized devices, anticipated the claims. Petitioner mapped Tanaka's p-type silicon substrate (10) and n-type diffused source/drain layers (11, 12). The "groove" etched into the substrate to house the gate electrode was argued to be the claimed "trench." Tanaka’s gate oxide layer (16), formed by thermal oxidation on the interior surfaces of the groove, was identified as the claimed "trench-to-gate insulating layer forming a contiguous layer." Petitioner contended that Tanaka’s subsequent deposition of a polysilicon film to form the gate electrode (15) within the groove met the final limitations of the independent claims.

Ground 3: Claims 1, 3, 11, and 13 are anticipated by Furukawa

  • Prior Art Relied Upon: Furukawa (Patent 5,998,835).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Furukawa, which describes a MOSFET device and manufacturing method featuring a gate trench, anticipated the claims. Furukawa disclosed a trench (370) etched into a silicon substrate (305) separating source/drain regions (310, 320). A channel (380) was formed at the bottom of the trench, contiguous with the source/drain regions via diffusion extensions (315, 325). Petitioner asserted that Furukawa's dielectric layer (330), which coated the trench’s sidewalls and bottom, directly corresponded to the claimed contiguous "trench-to-gate insulating layer." The subsequent deposition of a planarized polysilicon conductor (364) into the coated trench was argued to be the claimed "trenched gate electrode."

  • Additional Grounds: Petitioner asserted alternative obviousness challenges under 35 U.S.C. §103. These grounds argued that even if the primary references did not explicitly disclose every limitation, it would have been obvious for a person of ordinary skill in the art (POSITA) to adapt the teachings of Anderson, Tanaka, or Furukawa to arrive at the claimed invention. For claims reciting an "array of multiple device structures," Petitioner argued a POSITA would have been motivated to incorporate the individual transistor designs taught by the references into large-scale integrated circuits, such as DRAM memory chips, to achieve known benefits of device density and performance.

4. Key Claim Construction Positions

  • Petitioner argued for a construction of terms in dependent claims 4 and 14: "a trench spacer dielectric layer formed on the substantially upright vertical surfaces" and "a trench dielectric formed on the bottom surface."
  • Citing the doctrine of claim differentiation, Petitioner contended that because the corresponding independent claim recites a single "contiguous layer," these two limitations in the dependent claims must refer to dielectric layers that are formed separately. This construction was used to support Petitioner’s anticipation argument over Anderson, which discloses a multi-step process for forming insulating nitride sidewalls and a bottom gate oxide.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 3-4, 11, 13-14 of the ’061 patent as unpatentable.