PTAB

IPR2018-00365

SK Hynix Inc v. Netlist Inc

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Petition
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1. Case Identification

2. Patent Overview

  • Title: MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF OPERATION
  • Brief Description: The ’907 patent relates to a memory module, such as a Dual In-line Memory Module (DIMM), using distributed data buffers to mitigate increased electrical load that occurs when memory capacity is expanded. The invention aims to isolate the electrical load of memory devices from the system memory controller, thereby enabling higher capacity modules without degrading system performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Halbert and Amidi - Claims 30-57 are obvious over Halbert in view of Amidi.

  • Prior Art Relied Upon: Halbert (Patent 7,024,518) and Amidi (Application # 2006/0117152).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Halbert disclosed the foundational architecture of the challenged claims: a memory module with distributed buffers (which Halbert calls "interface circuits") to isolate the capacitive load of memory devices from the system memory data bus. Halbert’s interface circuit included a MUX/DeMUX creating a "fork-in-the-road" to route data to a selected memory rank while isolating the non-selected rank. Petitioner contended that Amidi taught a known, reliable method for increasing memory module capacity by using a Complex Programmable Logic Device (CPLD) to manage four ranks of memory while making the module appear as a standard two-rank module to the memory controller. The combination of Halbert’s load-isolating architecture with Amidi’s rank-doubling technique allegedly rendered the limitations of independent claims 30, 43, and 53 obvious.
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine Halbert and Amidi to achieve the well-understood goal of increasing memory capacity at a low cost. Halbert itself suggested that its architecture could be expanded to support more memory ranks, and Amidi provided a known, compatible technique for doing so transparently.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success, as the combination involved applying a standard rank-expansion technique (Amidi) to a compatible buffered memory architecture (Halbert) to achieve the predictable result of a higher-capacity, load-isolated module.

Ground 2: Obviousness over Halbert, Amidi, and Ruckerbauer - Claims 36 and 53-57 are obvious over Halbert and Amidi in further view of Ruckerbauer.

  • Prior Art Relied Upon: Halbert (Patent 7,024,518), Amidi (Application # 2006/0117152), and Ruckerbauer (Patent 7,334,150).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the primary Halbert/Amidi combination by incorporating the teachings of Ruckerbauer to satisfy limitations in claims 36 and 53 requiring a module control circuit with four distinct input/output connections to different subsets of memory devices. Petitioner asserted that while Halbert showed a T-bus for command signals, Ruckerbauer taught an improved topology where the register circuit is mounted centrally and drives separate command/address buses to the left and right sides of the module.
    • Motivation to Combine (for §103 grounds): A POSITA would be motivated to modify the Halbert/Amidi combination with Ruckerbauer’s separate bus structure to increase operating speeds and improve signal integrity, a known advantage of avoiding shared T-bus structures for high-speed signals.
    • Expectation of Success (for §103 grounds): Implementing Ruckerbauer's point-to-point bus topology within the Halbert/Amidi module was a straightforward design choice that used known components to achieve the predictable benefit of higher performance.

Ground 3: Obviousness over Halbert, Amidi, and Stone - Claims 45-57 are obvious over Halbert and Amidi in further view of Stone.

  • Prior Art Relied Upon: Halbert (Patent 7,024,518), Amidi (Application # 2006/0117152), and Stone (a 1982 book, "Microcomputer Interfacing").

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground added the teachings of Stone to the Halbert/Amidi combination to address claim limitations requiring separate "read data paths" and "write data paths" with tristate buffers (claims 45 and 53.f). Petitioner argued that while Halbert’s main embodiment used a bidirectional path, Stone, a foundational textbook, described the use of separate unidirectional paths with tristate buffers as a well-known technique for interfacing computer components.
    • Motivation to Combine (for §103 grounds): A POSITA would have recognized that implementing separate read/write paths as taught by Stone was a standard and well-known alternative to Halbert’s bidirectional path, offering a predictable way to manage data flow.
    • Expectation of Success (for §103 grounds): Designing unidirectional paths with tristate buffers for the Halbert/Amidi module would have been well within the skill of a POSITA, yielding the predictable result of a functional and efficient interface.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 31, adding Solomon (Application # 2006/0262586) to the Halbert/Amidi combination to explicitly teach configuring buffer circuits using known latency parameters (e.g., CAS latency) for timing data transfers.

4. Key Claim Construction Positions

  • "isolate memory device load": Petitioner proposed this term be construed to mean "electrically separate memory device load." This construction was argued to be consistent with a prior Board interpretation of a related patent and admissions from the Patent Owner's expert in parallel litigation.
  • "Fork-in-the-road" vs. "Straight-line" Interpretation: A central dispute involved the data path topology. Petitioner argued the ’907 patent disclosed a "fork-in-the-road" arrangement where different memory device groups are on separate data paths. In contrast, the Patent Owner allegedly advocated for a "straight-line" interpretation where the "first" and "second" memory devices are on the same data path. Petitioner contended that its invalidity arguments rendered the claims obvious under either interpretation.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 30-57 of the ’907 patent as unpatentable.