VIZIO, Inc. v. ATI Technologies ULC

1. Case Identification

• Case #: To Be Assigned
• Patent #: 7,796,133
• Filed: February 1, 2018
• Petitioner(s): VIZIO, Inc.
• Patent Owner(s): ATI Technologies ULC
• Challenged Claims: 1-13 and 40

2. Patent Overview

• Title: UNIFIED SHADER
• Brief Description: The ’133 patent is directed to a "unified shader" within a graphics processing pipeline. The shader is described as unified because it is configured to perform both color operations and texture operations using a single shading mechanism that comprises one or more Arithmetic Logic Unit (ALU)/memory pairs.

3. Grounds for Unpatentability

Ground 1: Claims 1, 8, and 13 are obvious over Alcorn in view of Jarvis

• Prior Art Relied Upon: Alcorn (Patent 5,185,856) and Jarvis (Patent 5,469,535).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Alcorn’s Pixel Cache/ALU 70 is a shader that satisfies most limitations of independent claim 1. It allegedly disclosed an input interface for receiving a packet of pixel data from a rasterizer (Scan Converter 30), a shading mechanism that performs both color and texture operations using ALU/memory pairs (AROP/BROP plus Pixel Caches), and an output interface to a frame buffer. Petitioner asserted that the combination with Jarvis, which discloses a graphics pipeline with a dedicated texture memory, supplies the remaining limitation of issuing a texture request to a texture unit and writing the received texture values back to memory.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Alcorn with Jarvis to implement the well-known method of using a dedicated texture unit for texture lookups. This would have been a natural modification, as Alcorn already taught a texture address generator, making the integration of Jarvis’s texture memory system a predictable design choice.
  • Expectation of Success: Petitioner asserted success would have been reasonably expected, as the combination involved applying a known technique from Jarvis to a known system from Alcorn to achieve a predictable improvement in function.

Ground 2: Claims 2 and 3 are obvious over Alcorn and Jarvis, in further view of Poulton

• Prior Art Relied Upon: Alcorn (Patent 5,185,856), Jarvis (Patent 5,469,535), and Poulton (Patent 5,481,669).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the base combination of Alcorn and Jarvis by adding Poulton to address the "valid-ready protocol" limitation recited in dependent claims 2 and 3. Petitioner argued that Poulton's "Ready-Go Protocol" is a known handshaking technique that explicitly discloses managing data transfer from a rasterizer to a shader (addressing claim 2) and from a shader to a frame buffer (addressing claim 3).
  • Motivation to Combine: A POSITA would incorporate Poulton's protocol to optimize and organize the data flow within the combined Alcorn/Jarvis graphics pipeline. Using such a handshaking protocol was a well-known solution to the common problem of synchronizing data transfer between different processing stages in a pipeline architecture.

Ground 3: Claims 4 and 5 are obvious over Alcorn and Jarvis, in further view of Papakipos

• Prior Art Relied Upon: Alcorn (Patent 5,185,856), Jarvis (Patent 5,469,535), and Papakipos (Patent 6,532,013).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground added Papakipos to the base combination to teach the "code partition mechanism" limitation of claim 4 and the grouping of code by "level of indirection" in claim 5. Petitioner contended that while Alcorn’s system is capable of multipass functions where intermediate results are reused, Papakipos explicitly teaches the claimed mechanism of partitioning shader code based on dependency ("levels of indirection") to properly execute such functions.
  • Motivation to Combine: Because Alcorn already contemplated multipass functionality, a POSITA would look to a reference like Papakipos for an established method to implement the necessary dependent coding and code partitioning. This modification would provide a concrete implementation for a feature already suggested in the primary reference.

• Additional Grounds: Petitioner asserted further obviousness challenges against claims 6-12 and 40. These grounds relied on the core Alcorn/Jarvis combination in further view of Rich (Patent 5,923,338) to teach a Single Instruction, Multiple Data (SIMD) architecture, a register subsystem, a pipelined memory structure, and a synchronized clock mechanism. Other arguments relied on the general knowledge of a POSITA to teach the use of state machines for control logic (claim 6). A separate ground argued claim 40 is obvious over a combination of Alcorn and Rich.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-13 and 40 of Patent 7,796,133 as unpatentable.