PTAB

IPR2018-00823

Texas Instruments Incorporated v. Complex Memory LLC

Title: Dynamic Random Access Memory (DRAM) with Integral Static Random Access Memory (SRAM)
Brief Description: The ’195 patent describes a memory system architecture featuring a DRAM main memory integrated with an SRAM that functions as a cache. The challenged method claims cover accessing data blocks by comparing a received address against values stored in latches (cache tags), accessing corresponding registers (cache data) on a match, and handling cache misses by exchanging data with the main memory array.

Prior Art Relied Upon: Fukuda (Patent 5,619,676) and Lin (Patent 5,423,019).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Fukuda taught a high-level memory system with the core functionalities of the ’195 patent, including a main memory ("memory cell arrays"), a cache ("cache memories"), and methods for handling cache hits and misses. Fukuda disclosed comparing an input address with stored tag addresses and, upon a miss, updating the cache with data from the main memory. It also taught a prefetching mechanism by predicting a subsequent address. This mapped to the primary steps of independent claim 6 and dependent claim 8, which adds serial access that Petitioner argued occurs naturally in some instances.
- Motivation to Combine: While Fukuda described a conceptual system, Lin provided specific, well-known implementation details. Lin taught using DRAM for main memory and SRAMs for both the cache tag memory and cache data memory. A POSITA would combine Lin's specific memory structures with Fukuda's conceptual architecture to implement an improved, high-speed memory system, a common goal in the art.
- Expectation of Success: This combination involved applying known techniques (Lin's memory types) to a known system (Fukuda's architecture) to achieve a predictable result.

Prior Art Relied Upon: Fukuda (Patent 5,619,676), Lin (Patent 5,423,019), and Matsuda (Patent 5,509,132).
Core Argument for this Ground:
- Prior Art Mapping: This ground built on the combination of Fukuda and Lin to address dependent claim 7, which adds the limitation of "accessing a plurality of locations in the register in response to a plurality of column addresses." While Fukuda/Lin established the use of an SRAM as the claimed "register," Matsuda explicitly taught the well-known method of accessing data within an SRAM using column address signals.
- Motivation to Combine: A POSITA implementing the Fukuda/Lin system would look to references like Matsuda for low-level implementation details, such as the addressing mechanism for the SRAM cache. Since all three references address improving cache memory performance, combining them was a natural design choice.
- Expectation of Success: Using column addresses to access SRAM was a standard, predictable technique, ensuring a high expectation of success in achieving the claimed functionality.

Prior Art Relied Upon: Smith (a 1982 paper titled Cache Memories) and Horowitz (a 1989 textbook titled The Art of Electronics).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner presented an alternative ground where Smith, a seminal paper on cache design, taught the fundamental principles of cache operation. Smith disclosed a cache with an "address array" (tags) and "data array" and a flowchart showing the process of receiving an address, comparing it to tags, handling hits, and managing misses by fetching data from main memory (cache eviction). Smith also taught prefetching.
- Motivation to Combine: Horowitz, a standard textbook, established the common knowledge of a POSITA, teaching that basic memory structures like latches, registers, and RAMs were well-known and often used interchangeably. A POSITA would have been motivated to implement the conceptual cache system of Smith using the standard components and structures described in Horowitz as a matter of routine design.
- Expectation of Success: The combination represented the simple application of basic electronic components (from Horowitz) to a well-understood architecture (from Smith), which would predictably result in a functioning cache system.

Prior Art Relied Upon: Smith, Horowitz, and Matsuda (Patent 5,509,132).
Core Argument for this Ground:
- Prior Art Mapping: This ground built on the Smith/Horowitz combination to address claim 7. As in Ground II, Petitioner argued Matsuda supplied the necessary teaching of accessing locations within the SRAM-based register using a plurality of column addresses.
- Motivation to Combine: A POSITA building a cache based on the Smith/Horowitz combination would have been motivated to consult a reference like Matsuda to implement the specific addressing scheme for the SRAM cache registers, as this was a common design consideration.
- Expectation of Success: The combination was a straightforward application of a known addressing technique (Matsuda) to a standard cache component (the SRAM register from the Smith/Horowitz combination), yielding predictable results.

Petitioner argued that for the purposes of the IPR, it adopted the Patent Owner's apparent interpretation of the term "exchanging" from the related litigation. This interpretation construed "exchanging" to mean the cache eviction process that occurs after a "cache miss," where data from the main memory array replaces or is substituted for data in the cache registers and latches.

A central technical argument was that the terms "registers," "latches," and "SRAMs" were well-understood by a POSITA to be functionally similar and interchangeable for building cache memories. Petitioner supported this by pointing to the ’195 patent's own disclosure and the Patent Owner's infringement contentions, which equated the accused products' "data RAM" with the claimed "registers" and "tag RAM" with the claimed "latches."

Petitioner argued that institution was proper under 35 U.S.C. §325(d) because neither the prior art references nor the specific invalidity arguments presented in the four grounds were the same or substantially the same as those previously considered by the PTO during original prosecution.

Petitioner requested the institution of an inter partes review and the cancellation of claims 6-8 of Patent 5,890,195 as unpatentable under 35 U.S.C. §103.