PTAB

IPR2018-01155

Intel Corp v. Godo Kaisha IP Bridge 1

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petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with Constant Dimension Gate Conductor to Mitigate Optical Proximity Effect
  • Brief Description: The ’900 patent discloses a semiconductor device layout intended to solve fabrication distortions caused by the "optical proximity effect." The invention uses a linear gate conductor film with a substantially constant dimension in the gate length direction, combined with a gate contact that is larger than the gate conductor and located over an element isolation region rather than the active region, which allegedly prevents undesirable rounding during fabrication.

3. Grounds for Unpatentability

Ground 1: Obviousness over Maeda and Wieczorek - Claims 1-4 and 10 are obvious over Maeda in view of Wieczorek.

  • Prior Art Relied Upon: Maeda (Japanese Unexamined Patent Appl. Pub. S62-217635) and Wieczorek (6,566,718).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Maeda, a 1986 Japanese application describing an NMOS semiconductor device, disclosed the core features of independent claim 1. Specifically, Maeda's gate electrode 6 was described as a linear gate conductor film with a substantially constant dimension, formed across an active region (region 3 and 4) and an element isolation region (field oxide film 2). Further, Maeda's contact hole 13 was disclosed as being wider than gate electrode 6 and connected to the gate electrode over the isolation region, not the active region. Petitioner contended that Wieczorek was cited to supplement any potential deficiencies in Maeda, teaching, for example, the use of shallow trench isolations to fully surround an active region. For dependent claim 10, Wieczorek was cited for its explicit disclosure of sidewall spacers 207 on the side surfaces of a gate electrode, a common feature in semiconductor design.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the teachings of Maeda and Wieczorek because both references are in the same field of semiconductor design and utilize linear layouts with oversized contacts. Petitioner asserted that implementing Wieczorek’s well-known and standard isolation techniques and sidewall spacers into Maeda’s fundamental design was a predictable step to improve electrical isolation and device performance. These modifications addressed known problems and were common practice at the time.
    • Expectation of Success: A POSITA would have a high expectation of success, as the combination involved integrating standard, well-understood components and manufacturing processes (such as shallow trench isolation and sidewall spacers) into a conventional transistor layout.

Ground 2: Obviousness over Maeda, Wieczorek, and Gheewalla - Claims 5-9 are obvious over Maeda, Wieczorek, and Gheewalla.

  • Prior Art Relied Upon: Maeda, Wieczorek, and Gheewalla (5,723,883).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the Maeda/Wieczorek combination to challenge claims directed to complementary metal-oxide-semiconductor (CMOS) structures. Petitioner argued that Maeda taught a paired-transistor NMOS design. Gheewalla was introduced because it taught using PMOS and NMOS transistors together in a CMOS layout, which was the industry standard by the ’900 patent’s priority date. Petitioner contended that modifying Maeda’s paired NMOS design to a CMOS design by replacing one NMOS transistor with a PMOS transistor as taught by Gheewalla would render claim 7 (requiring P-type and N-type transistors in separate active regions) obvious. This modification would also render claim 5 obvious, as the gate interconnect over the N-type and P-type transistors would correspondingly comprise N-type and P-type polysilicon films. Claims 6, 8, and 9 were argued to be obvious by extending this CMOS pair into a larger cell architecture, as also taught by Gheewalla.
    • Motivation to Combine: A POSITA would be motivated to incorporate Gheewalla's CMOS teachings into the Maeda/Wieczorek design to gain the well-known benefits of CMOS technology, such as lower power consumption and higher noise immunity, which were significant advantages over older NMOS-only designs. All three references concern MOS transistors and linear layouts, making the integration of Gheewalla's established CMOS architecture a logical progression.
    • Expectation of Success: Modifying an NMOS pair to a CMOS pair was a routine and well-known modification in semiconductor design. The process involved predictable changes in dopants and layouts, and a POSITA would have reasonably expected the resulting structure to function as intended.

Ground 3: Obviousness over Chakihara - Claims 1-4 are obvious over Chakihara.

  • Prior Art Relied Upon: Chakihara (7,190,031).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Chakihara, a more modern reference directed to semiconductor memory, rendered claims 1-4 obvious on its own. Chakihara allegedly disclosed all elements of independent claim 1, including island-shaped active regions L surrounded by device isolation trenches 2. Chakihara’s gate electrode 7B was described as a linear conductor with a constant dimension formed across both the active and isolation regions. Petitioner highlighted that Chakihara's contact holes 22 were shown to be larger than the gate electrode in the gate length direction and were connected to the gate electrode over the isolation trenches, but not over the active region. This mapping was argued to satisfy every limitation of claim 1, including the critical negative limitation that the contact is not connected over the active region.
    • Motivation to Combine (N/A): As this ground is based on a single reference, Petitioner argued that Chakihara alone disclosed a structure that made the claimed invention obvious without any need for combination or modification.

4. Relief Requested

  • Petitioner requests institution of inter partes review (IPR) and cancellation of claims 1-10 as unpatentable.