Apple Inc v. Qualcomm Inc

1. Case Identification

• Case #: IPR2018-01285
• Patent #: 9,024,418
• Filed: July 27, 2018
• Petitioner(s): Apple Inc.
• Challenged Claims: 1, 2, 4, 5, 7, 8, 11-13, and 15-20

2. Patent Overview

• Title: Local Interconnect Structures For High Density
• Brief Description: The ’418 patent disclosed electronic circuit implementations for high-density, sub-micron semiconductor processes. The technology aimed to improve circuit density and performance by providing a novel local interconnect architecture for coupling transistors, which overcomes layout constraints associated with conventional methods that use blocking transistors for isolation.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 4, 8, 11-13, 15, and 17-20 are obvious over Yoshida in view of Liaw.

• Prior Art Relied Upon: Yoshida (Patent 8,026,536) and Liaw (Application # 2009/0014796).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Yoshida taught a high-density semiconductor device (a ring oscillator) that used a regular gate array structure with dummy gate electrodes between transistors to optimize layout and reduce parasitic capacitance. This structure allegedly met most limitations of independent claim 1, including multiple gate layers arranged at a pitch and gate-directed interconnects. However, Yoshida disclosed but did not detail the specific interconnects used to connect its dummy gate electrodes to the source regions. Liaw was argued to supply this missing element by teaching an improved contact structure with a "diffusion-directed" contact (CONT2 16) for connecting a gate of one transistor to a source/drain region of a neighboring transistor.
  • Motivation to Combine: A POSITA would combine Liaw's well-defined, diffusion-directed contact structure with Yoshida’s layout to implement the connections that Yoshida described but did not illustrate. This combination would serve to optimize the contact and interconnect implementation in Yoshida's design, thereby improving device performance and reliability by using a known, advantageous contact structure.
  • Expectation of Success: The combination represented a predictable application of a known interconnect technique (Liaw) to a similar device (Yoshida) to achieve expected improvements in device performance.

Ground 2: Claim 7 is obvious over Yoshida in view of Liaw and Lin.

• Prior Art Relied Upon: Yoshida (Patent 8,026,536), Liaw (Application # 2009/0014796), and Lin (Patent 5,376,585).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Yoshida and Liaw combination to address claim 7, which added the limitation that the gate-directed and diffusion-directed local interconnects all comprise tungsten. The base circuit structure was provided by the combination of Yoshida and Liaw. Lin was introduced because it explicitly taught a method for manufacturing local interconnects using tungsten, noting the process was cost-effective, reliable, and compatible with existing fabrication methods.
  • Motivation to Combine: A POSITA would be motivated to form the interconnects of the Yoshida-Liaw combination using the tungsten process described in Lin. The motivation was to gain the known advantages taught by Lin, such as improved manufacturing yield, lower cost, and higher reliability, which were common goals in semiconductor fabrication.
  • Expectation of Success: Fabricating a known interconnect structure with a known and suitable material like tungsten was a simple substitution that a POSITA would have undertaken with a high expectation of success.

Ground 3: Claims 5 and 16 are obvious over Yoshida in view of Liaw and Chen.

• Prior Art Relied Upon: Yoshida (Patent 8,026,536), Liaw (Application # 2009/0014796), and Chen (Patent 6,818,547).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed claims 5 and 16, which added limitations related to a via coupled between a first metal layer and the interconnects. While Liaw mentioned using a dual damascene process (which implies vias) to form its interconnects, it did not provide details. Chen was asserted to cure this by disclosing a detailed dual damascene process for manufacturing multilevel interconnects, explicitly teaching the formation of vias to connect conductive layers. The combination of Yoshida, Liaw, and Chen was argued to teach a circuit with a via coupling a metal layer to an interconnect to provide power, as required by the claims.
  • Motivation to Combine: A POSITA, seeking to implement the multilevel interconnect structure suggested by the Yoshida and Liaw combination, would turn to a well-known, reliable process like the dual damascene method taught by Chen. Chen’s process provided an explicit and advantageous method for creating the necessary vias, promising higher product yield and reliability.
  • Expectation of Success: Combining the teachings was predictable, as it involved using a standard, predominant fabrication process (Chen) to implement a structural feature (vias) that was already implicitly required for the multilevel interconnects of the primary references.

4. Key Claim Construction Positions

• "means for coupling" (claims 17-19): Petitioner contended that under 35 U.S.C. §112, para. 6, this term corresponds to the "diffusion-directed local interconnect" structure and its equivalents as disclosed in the ’418 patent’s specification and figures.
• "continuous diffusion region" (claims 2, 4, 15, 17-20): Petitioner argued this term should be construed to mean a diffusion region that does not include any isolation region (e.g., shallow trench isolation). This construction was critical for mapping Yoshida’s transistor layout, which used dummy gate electrodes rather than isolation regions to separate adjacent transistors within a common diffusion area.

5. Relief Requested

• Petitioner requests the institution of an inter partes review and cancellation of claims 1, 2, 4, 5, 7, 8, 11-13, and 15-20 of the ’418 patent as unpatentable.