PTAB

IPR2018-01312

Intel Corp v. VLSI Technology LLC

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petition

1. Case Identification

2. Patent Overview

  • Title: Power Management for Cache Memory
  • Brief Description: The ’014 patent discloses a device and method for power management, specifically for reducing power consumption in a cache memory during a low power mode. The invention determines whether to power down a portion of a component based on a relationship between an estimated power gain and an estimated power loss.

3. Grounds for Unpatentability

Ground I: Obviousness over Takahashi - Claims 12-14, 18, and 20 are obvious over Takahashi.

  • Prior Art Relied Upon: Takahashi (Patent 5,761,715).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Takahashi taught all limitations of the challenged claims. Takahashi described an information processing device that reduces power consumption by selectively powering down individual cache "ways" (portions of the cache). The decision to power down a way was made by a "way number control circuit" (the claimed "power management circuitry") which compared a measured cache-miss rate to a predetermined threshold. This comparison, Petitioner asserted, represented the claimed "relationship between an estimated power gain and an estimated power loss," where the cache-miss rate served as a proxy for power loss (since misses increase power consumption) and the threshold served as a proxy for power gain (the power saved by turning off a way).
    • Key Aspects: This ground asserted that the core concept of the ’014 patent—using a proxy-based comparison to manage power—was not novel and was fully disclosed within a single prior art reference that addressed the identical technical problem.

Ground II: Obviousness over Takahashi and Hu - Claims 12-14, 18, and 20 are obvious over Takahashi in view of Hu.

  • Prior Art Relied Upon: Takahashi (Patent 5,761,715) and Hu (a May 2002 journal article titled "Let Caches Decay...").
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Takahashi's foundational disclosure of a device with individually powered cache portions. Petitioner argued that Hu explicitly taught the one element that was only implicitly taught by proxy in Takahashi: determining whether to power down a cache portion based on an explicit comparison of estimated power gain and loss. Hu disclosed measuring the static power saved by turning off cache lines (power gain) and comparing it to the extra dynamic power dissipated due to additional cache misses (power loss). Hu's method used a ratio ("L2Access:leak") to quantify this relationship and determine the optimal time to power down a cache line.
    • Motivation to Combine: A POSITA would combine these references because both addressed the identical problem of reducing power consumption in cache memory. A POSITA seeking to improve Takahashi's proxy-based system would have been motivated to incorporate Hu's more direct and quantitative method of balancing explicit power gains and losses to achieve a more efficient power-saving technique.
    • Expectation of Success: Modifying Takahashi's system to replace its cache-miss rate proxy with Hu's explicit calculation of power gain versus power loss would have been a routine design choice. This would predictably result in a more optimized system that only powers down a cache way when the estimated power gain is greater than the estimated power loss, which was the explicit goal of both references.

Ground III: Obviousness over Takahashi and Gunther - Claim 20 is obvious over Takahashi in view of Gunther.

  • Prior Art Relied Upon: Takahashi (Patent 5,761,715) and Gunther (Patent 5,781,783).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground specifically targeted claim 20, which added limitations requiring the device to "monitor integrated circuit behavior" and for the power-down determination to be "responsive to results of the monitoring." While Takahashi monitored the cache-miss rate, Petitioner argued Gunther provided more explicit teachings. Gunther disclosed a power control circuit with "circuit block activity monitoring logic" that monitored events like L1 cache hits/misses or periods of inactivity to predict future behavior. Based on this monitoring, Gunther's device determined whether to power down a circuit block.
    • Motivation to Combine: A POSITA would combine Gunther's advanced monitoring techniques with Takahashi's power-saving framework to improve performance. Gunther explained that monitoring circuit behavior, such as L1 cache hits, allows a system to speculatively predict future memory access needs, providing a better basis for power-down decisions. Incorporating this into Takahashi would be a logical step to enhance the system's efficiency.
    • Expectation of Success: Integrating Gunther's monitoring logic into Takahashi's device was presented as a predictable combination of known elements. A POSITA would expect that using more sophisticated monitoring to inform the power-down decision would lead to the expected result of improved power management.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 20 based on the combination of Takahashi, Hu, and Gunther, which relied on similar design modification theories.

4. Relief Requested

  • Petitioner requests institution of IPR and cancellation of claims 12-14, 18, and 20 of Patent 8,020,014 as unpatentable.