PTAB

IPR2018-01353

Apple Inc v. Qualcomm Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: LOCAL INTERCONNECT STRUCTURES FOR HIGH DENSITY
  • Brief Description: The ’418 patent discloses electronic circuit architectures designed to increase circuit density in sub-micron manufacturing processes. The technology addresses challenges in strain engineering by using blocking transistors to isolate neighboring transistors within a continuous diffusion region, coupled with a multi-level local interconnect scheme.

3. Grounds for Unpatentability

Ground 1: Obviousness over Yoshida in view of Rashed 910 - Claims 1-2, 4-6, 8, 11-13, and 15-20 are obvious over Yoshida in view of Rashed 910.

  • Prior Art Relied Upon: Yoshida (Patent 8,026,536) and Rashed 910 (Patent 9,355,910).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Yoshida and Rashed 910 taught all limitations of the challenged claims.
      • Yoshida discloses a high-density semiconductor device (a ring oscillator) with a gate array structure that improves layout efficiency. It teaches using transistors (e.g., PMOS 14-1, 14-2) arranged in a continuous diffusion region and separated by "dummy gate electrodes" (e.g., 12a). Petitioner asserted these dummy gates, which are tied to a common power source to isolate adjacent transistors, are analogous to the "blocking transistor" of the ’418 patent. Yoshida further discloses "first-layer" source and drain lines (e.g., 17a, 17b) that function as gate-directed local interconnects, as they run parallel to the gate electrodes.
      • Rashed 910 addresses the need for efficient cross-coupling of transistors using local interconnects that conserve semiconductor area. It explicitly teaches a multi-level interconnect scheme with layers disposed between the substrate and the first metal layer. Specifically, Rashed 910 discloses a gate-directed interconnect layer (CA layer 34) and a diffusion-directed interconnect layer (CB layer 36) that is orthogonal to the gate electrodes. This CB layer is used to connect a gate electrode to a source/drain region via the CA layer.
    • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would have been motivated to combine the teachings of Yoshida and Rashed 910. Yoshida teaches that its dummy gates are connected to source regions using "interconnects not shown," leaving the specific implementation open. Rashed 910 provides a known and advantageous solution for this exact purpose: using a diffusion-directed interconnect (CB layer) to connect a gate to a source/drain region. A POSITA would have looked to a reference like Rashed 910 to implement Yoshida’s conceptual connections in a space-efficient manner, thereby optimizing the layout of Yoshida's high-density structure. This combination amounted to applying a known technique from Rashed 910 to improve a similar device in Yoshida to achieve predictable results.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in this combination. Both references operate in the same field of semiconductor layout and interconnects, and the proposed modification involves integrating a specific, well-defined interconnect structure from Rashed 910 into the clearly disclosed gate array of Yoshida. The result would be a predictable improvement in layout density and performance.

4. Key Claim Construction Positions

  • "means" for coupling (claims 17-19): Petitioner proposed this term should be construed to encompass the corresponding structure disclosed in the specification, which is a "diffusion-directed local interconnect." This construction was critical for mapping the diffusion-directed CB interconnect layer from Rashed 910 onto this claim limitation.
  • "continuous" diffusion region (claims 2-4, 9, 14, 15, 17-20): Petitioner argued this term should be construed as "a diffusion region that does not include any isolation region," such as shallow trench isolation (STI) or LOCOS. This construction was important for establishing that Yoshida’s layout, which uses dummy gates for isolation within a shared diffusion area rather than conventional isolation structures, meets the claim limitation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-2, 4-6, 8, 11-13, and 15-20 of the ’418 patent as unpatentable.