PTAB

IPR2018-01353

Apple Inc. v. Qualcomm Incorporated

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1. Case Identification

  • Case #: IPR2018-01353
  • Patent #: 9,024,418
  • Filed: July 27, 2018
  • Petitioner(s): Apple Inc.
  • Challenged Claims: 1, 2, 4-6, 8, 11-13, 15-20

2. Patent Overview

  • Title: Local Interconnect Structures for High Density
  • Brief Description: The ’418 patent discloses electronic circuit implementations intended to address design challenges in high-density, sub-micron circuits. The technology focuses on using specific local interconnect structures to couple transistors, including blocking transistors, within a continuous diffusion region to increase layout density and improve performance compared to conventional designs.

3. Grounds for Unpatentability

Ground 1: Obviousness over Yoshida and Rashed 910 - Claims 1, 2, 4-6, 8, 11-13, and 15-20 are obvious over Yoshida in view of Rashed 910.

  • Prior Art Relied Upon: Yoshida (Patent 8,026,536) and Rashed 910 (Patent 9,355,910).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Yoshida teaches the fundamental layout of a high-density semiconductor device, specifically a ring oscillator, that uses a repeating gate array structure to optimize layout and reduce parasitic capacitance. Yoshida’s design includes transistors formed in continuous diffusion regions (lacking traditional isolation trenches) and uses "dummy" gate electrodes between active transistors that function as the "blocking transistors" recited in the ’418 patent claims. However, Petitioner contended that Yoshida is not specific about the interconnects used to connect these dummy gates to source regions.

      Petitioner asserted that Rashed 910 remedies this by disclosing a specific and efficient method for creating local interconnects between transistors. Rashed 910 teaches using two types of local interconnect layers: a gate-directed layer ("CA layer") and a diffusion-directed layer ("CB layer") that runs orthogonally to the gate direction. These interconnects are located between the semiconductor substrate and the first metal layer, providing a space-saving way to cross-couple transistor terminals.

      The combination allegedly meets the limitations of independent claim 1. Yoshida provides the circuit with a first (blocking), second, and third gate layer arranged at a pitch. Yoshida also discloses first and second gate-directed local interconnects (first-layer source and drain lines). Rashed 910 provides the claimed "diffusion-directed local interconnect layer" (its CB layer) configured to couple the first gate layer (Yoshida’s dummy gate) to one of the gate-directed interconnects (Yoshida's source line). Finally, Rashed 910 teaches that these local interconnects are located below the lower-most metal layer, satisfying the final limitation of claim 1. Arguments for dependent claims followed from this primary combination.

    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would be motivated to combine the teachings of these references. A POSITA looking to implement Yoshida’s dense circuit layout would recognize the need for an efficient interconnect scheme to make the connections Yoshida describes but does not detail. Rashed 910 provides a known, space-saving solution for this exact problem. Therefore, a POSITA would combine Rashed 910's interconnect technique with Yoshida's transistor layout to achieve the predictable result of a compact, high-performance circuit.

    • Expectation of Success: A POSITA would have had a reasonable expectation of success in making this combination. Both patents operate in the same field of semiconductor design and layout. Applying a known interconnect method (Rashed 910) to a known transistor array architecture (Yoshida) was a routine design choice that would be expected to work as intended.

4. Key Claim Construction Positions

  • "means for coupling" (claims 17-19): Petitioner argued this term should be construed as the corresponding structure disclosed in the ’418 patent specification, which is a "diffusion-directed local interconnect." This construction was critical for mapping the diffusion-directed CB layer from Rashed 910 onto the limitations of the means-plus-function claims.
  • "continuous diffusion region" (claims 2-4, 9, 14, 15, 17-20): Petitioner proposed this term encompasses a diffusion region that does not include any isolation regions, such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS). This interpretation was important for demonstrating how Yoshida, which uses dummy gate electrodes for isolation rather than dedicated isolation regions, discloses a "continuous diffusion region" as claimed.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 2, 4-6, 8, 11-13, and 15-20 of Patent 9,024,418 as unpatentable.