PTAB
IPR2018-01377
BlueHouse Global Ltd v. Semiconductor Energy Laboratory Co Ltd
Key Events
Petition
Table of Contents
petition
1. Case Identification
- Case #: IPR2018-01377
- Patent #: 9,281,405
- Filed: July 10, 2018
- Petitioner(s): Bluehouse Global Ltd.
- Patent Owner(s): Semiconductor Energy Laboratory Co., Ltd.
- Challenged Claims: 10, 11, 15, and 16
2. Patent Overview
- Title: Semiconductor Device and Method for Manufacturing the Same
- Brief Description: The ’405 patent discloses a semiconductor device, specifically a thin-film transistor (TFT), featuring a multi-layered structure. The structure includes stacked conductive layers forming source and drain electrodes, where the distance between the lower conductive layers is shorter than the distance between the upper layers.
3. Grounds for Unpatentability
Ground 1: Anticipation of Claims 10, 11, 15, and 16 under 35 U.S.C. §102(b)
- Prior Art Relied Upon: Godo (Application # 2011/0193081).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Godo anticipates every limitation of the challenged claims. Godo’s FIG. 1B and accompanying text allegedly disclosed a bottom-gate TFT with the same layered structure as independent claim 10: a gate electrode (148), gate insulating layer (146), oxide semiconductor layer (144a), and source/drain electrodes (141a/141b). Petitioner asserted that Godo's source and drain electrodes were composed of two stacked conductive layers (145a/142a and 145b/142b), corresponding to the claimed first/third and second/fourth conductive layers. Crucially, Petitioner contended that a magnification of Godo's FIG. 1B demonstrated that the distance between the lower conductive layers (145a, 145b) is shorter than the distance between the upper layers (142a, 142b). For dependent claim 11, Petitioner argued Godo explicitly taught using an In-Ga-Zn-O based oxide for the semiconductor layer, satisfying the claimed composition. For claims 15 and 16, Godo’s structure inherently placed the semiconductor layer over the gate electrode and disclosed a "protective insulating layer" formed over the transistor, respectively.
Ground 2: Anticipation of Claims 10, 15, and 16 under 35 U.S.C. §102(b)
- Prior Art Relied Upon: Toyota (Application # 2008/0299693).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Toyota’s FIG. 8B disclosed a semiconductor device that identically meets the limitations of claims 10, 15, and 16. Toyota allegedly showed a bottom-gate TFT with a gate electrode (GT), an insulating film (GI), a semiconductor layer (PS), and source/drain electrodes (ST/DT). Petitioner contended that Toyota's source and drain electrodes were layered products of lower (ST(D)/DT(D)) and upper (ST(U)/DT(U)) conductive layers, corresponding to the claimed first/third and second/fourth layers. The petition asserted that Toyota's teaching that the lower electrodes "protrude outward" from the upper electrodes necessarily meant the distance between the lower electrodes was shorter than the distance between the upper electrodes, meeting a key limitation of claim 10. For dependent claims, the sequential stacking shown in Toyota’s FIG. 8B inherently located the semiconductor layer over the gate electrode (claim 15), and Toyota explicitly disclosed forming a "protective coat PAS" over the device (claim 16).
Ground 3: Obviousness of Claim 11 under 35 U.S.C. §103(a)
- Prior Art Relied Upon: Toyota (Application # 2008/0299693) in view of Godo (Application # 2011/0193081).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that claim 11 would have been obvious over the combination of Toyota and Godo. Toyota was asserted to teach every limitation of base claim 10, as detailed in Ground 2. However, Toyota did not disclose the specific semiconductor composition required by dependent claim 11 (an oxide including In, an element M, and Zn). Godo allegedly supplied this missing element by explicitly teaching the use of various oxide semiconductors, including In-Ga-Zn-O, In-Sn-Zn-O, and In-Al-Zn-O-based oxides, all of which fall within the generic formula of claim 11.
- Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings because Godo provides a clear reason to replace the semiconductor material in a device like Toyota’s. Godo taught that using an oxide semiconductor results in a significantly lower off-state current (leakage current) compared to a conventional silicon semiconductor. A POSITA would therefore be motivated to incorporate Godo’s superior oxide semiconductor material into Toyota’s known TFT structure to improve device performance by reducing leakage.
- Expectation of Success: A POSITA would have had a reasonable expectation of success in making this substitution, as it involved replacing one known type of semiconductor material with another known type to achieve a predictable improvement (reduced leakage current) in a standard TFT architecture.
4. Relief Requested
- Petitioner requests institution of an inter partes review and cancellation of claims 10, 11, 15, and 16 of the ’405 patent as unpatentable.
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