PTAB

IPR2018-01377

Bluehouse Global Ltd. v. Semiconductor Energy Laboratory Co., Ltd.

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1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device and Method for Manufacturing the Same
  • Brief Description: The ’405 patent discloses a semiconductor device, specifically a thin-film transistor (TFT), featuring a multi-layered structure. The device includes a gate electrode, an oxide semiconductor layer, and source/drain electrodes each composed of two stacked conductive layers, with specific geometric relationships between the layers.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 10, 11, 15, and 16 - Claims are anticipated under pre-AIA 35 U.S.C. §102(b) by Godo.

  • Prior Art Relied Upon: Godo (Application # 2011/0193081).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Godo discloses every element of the challenged claims. Independent claim 10 recites a TFT with a specific layered structure, including a gate electrode, insulating layer, semiconductor layer, and source/drain electrodes each comprised of two conductive layers. Petitioner contended that Godo’s FIG. 1B and accompanying text disclose an identical structure, mapping Godo’s gate electrode (148), gate insulating layer (146), and oxide semiconductor layer (144a) directly to the claim elements. Critically, Godo's source electrode (141a) and drain electrode (141b) are shown as two-layer stacks (145a/142a and 145b/142b, respectively), which Petitioner mapped to the claimed first/third and second/fourth conductive layers. Godo was also argued to teach the two key wherein clauses of claim 10: that the distance between the lower conductive layers (145a, 145b) is shorter than the distance between the upper conductive layers (142a, 142b), and that these stacked layers function as the source and drain electrodes.
    • For the dependent claims, Petitioner asserted that Godo explicitly teaches the specific oxide semiconductor materials required by claim 11 (e.g., In-Ga-Zn-O), the required location of the semiconductor layer over the gate electrode (claim 15), and the use of a "protective insulating layer" (claim 16).

Ground 2: Anticipation of Claims 10, 15, and 16 - Claims are anticipated under pre-AIA 35 U.S.C. §102(b) by Toyota.

  • Prior Art Relied Upon: Toyota (Application # 2008/0299693).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner presented an alternative anticipation challenge using Toyota. It was argued that Toyota’s FIG. 8B discloses a bottom-gate TFT that meets all limitations of claim 10. The petition mapped Toyota’s gate electrode (GT), gate insulating film (GI), and semiconductor layer (PS) to the corresponding claim elements. The source electrode (ST) and drain electrode (DT) in Toyota are disclosed as layered products of lower (ST(D), DT(D)) and upper (ST(U), DT(U)) electrodes. Petitioner contended these structures correspond to the claimed first/third and second/fourth conductive layers.
    • Further, Petitioner argued that Toyota’s disclosure that the lower electrodes protrude outward from the upper electrodes inherently teaches the claimed geometric relationship where the distance between the lower electrodes is shorter than the distance between the upper electrodes. The petition also identified Toyota's protective coat (PAS) made of resin as the claimed "first insulating layer." The arguments for dependent claims 15 (semiconductor location) and 16 (protective layer function) followed the mapping for the independent claim.

Ground 3: Obviousness of Claim 11 - Claim 11 is obvious under pre-AIA 35 U.S.C. §103(a) over Toyota in view of Godo.

  • Prior Art Relied Upon: Toyota (Application # 2008/0299693) and Godo (Application # 2011/0193081).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Toyota discloses every limitation of base claim 10. The only distinction for dependent claim 11 is its requirement for a specific semiconductor material: an oxide including Indium (In), Zinc (Zn), and an element M (such as Gallium, Tin, or Aluminum). While Toyota’s primary embodiment may use a different semiconductor, Godo was introduced because it explicitly teaches the benefits of using these specific oxide materials (e.g., In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O) as the semiconductor layer in a TFT.
    • Motivation to Combine: The motivation to combine was based on improving device performance. Godo explicitly teaches that transistors using an oxide semiconductor have an off-state current that is orders of magnitude smaller than transistors using a silicon semiconductor, resulting in negligible leakage current. A person of ordinary skill in the art (POSITA) reviewing Toyota’s TFT design would therefore be motivated to replace its semiconductor layer with one of the superior oxide semiconductor materials taught by Godo to achieve the known and desirable benefit of reduced power consumption and improved performance.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in making this combination. The proposed modification was a simple substitution of one known type of semiconductor material for another in a conventional TFT architecture to achieve a predictable result (reduced leakage current) that was explicitly taught by the secondary reference, Godo.

4. Relief Requested

  • Petitioner requested that the Board institute an inter partes review (IPR) of claims 10, 11, 15, and 16 of the ’405 patent and cancel those claims as unpatentable.