PTAB

IPR2018-01720

Samsung Electronics Co Ltd v. BiTMICRO LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Module with Serial Chain Routing
  • Brief Description: The ’243 patent discloses a stacked module system, such as for memory scalability, that uses a specific serial chain architecture for routing signals. The invention focuses on a method for testing interconnections in the stack using two distinct serial chain routes and a control circuit in an "end module" that can selectively connect them, akin to a JTAG (Joint Test Action Group) daisy-chain configuration.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 11, and 12 are obvious over Sato.

  • Prior Art Relied Upon: Sato (International Publication No. WO 2004/072667).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sato discloses all elements of the challenged claims. Sato teaches a stack of memory modules with a JTAG boundary scan test performed in a "daisy chain" configuration. This primary TDI/TDO (Test Data In/Test Data Out) daisy chain, which propagates up the stack, constitutes the claimed "first serial chain route." Sato further discloses a second signal path, TDO2, that passes down the stack, which Petitioner mapped to the "second serial chain route." Crucially, Sato's control logic in the uppermost module (the "end module") includes comparison means and a tri-state buffer. This control circuit determines it is the top module and enables a "routing path" that connects the TDI input (from the first route) to the TDO2 output (to the second route), thereby satisfying the central limitations of independent claim 1. For dependent claim 2, Petitioner asserted Sato's vertical "penetrating electrodes" combined with horizontal connection lines form the claimed "ladder-like routing path."
    • Key Aspects: Petitioner contended that a person of ordinary skill in the art (POSITA) would have understood Sato's "memory chip" to include SDRAM, a common memory type, thus addressing an implicit feature of the claims.

Ground 2: Claims 1, 2, 11, and 12 are obvious over Sato in view of Gaynes.

  • Prior Art Relied Upon: Sato (WO 2004/072667) and Gaynes (Patent 6,236,115).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground reinforces the arguments based on Sato, with Gaynes added to explicitly teach certain structural details if Sato is deemed insufficient. Petitioner argued that if the claimed "active port" and "passive port" are construed to require specific ball-and-pad structures, Gaynes provides the missing disclosure. Gaynes teaches a method for creating interconnections in stacked memory modules using through-silicon vias (TSVs), conductive pads (surface deposits), and solder balls. These structures in Gaynes directly map to the claimed port, ball, and pad limitations.
    • Motivation to Combine: A POSITA looking to implement Sato's stacked architecture would combine it with well-known and advantageous interconnection methods like those in Gaynes. Gaynes offered a practical and detailed method for fabricating the TSVs, pads, and balls used to connect stacked modules, providing benefits such as enhanced durability and electrical performance.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because both Sato and Gaynes operate in the same technical field of stacked semiconductor chips and describe compatible interconnection technologies (vertical vias). Implementing Sato’s JTAG architecture using Gaynes’s specific ball-and-pad TSV structures would be a predictable combination of known elements for a known purpose.

Ground 3: Claims 1, 2, 11, and 12 are obvious over Sung.

  • Prior Art Relied Upon: Sung (Application # 2003/0178228).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner presented Sung as an alternative primary reference that discloses a three-dimensional stacked integrated circuit system anticipating all claim limitations. Sung’s "inter-die scan chain" that communicates between multiple dies was mapped to the claimed "first serial chain route." A separate "broadcasting circuit" that conveys data from the bottom to the top of the stack was mapped to the "second serial chain route." Sung’s bottom-most module functions as the "end module" and contains a "die identifier circuit" and a "tristate buffer." This control circuit detects its position at the bottom of the stack and enables a routing path connecting the inter-die scan chain (first route) to the broadcasting circuit (second route).
    • Key Aspects: Petitioner argued that Sung's control logic operates identically to that described in the ’243 patent, where a grounded signal from an adjacent module disables the routing path, while the absence of an adjacent module (at the end of the stack) allows a pull-up voltage to enable it.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that the claims are obvious over Sato in view of Eide (Patent 5,612,570) and over Sung in view of Matsui (Application # 2004/0257847). The combination with Eide was used to explicitly teach stacking memory chips mounted on PCB substrates. The combination with Matsui was used to explicitly teach the use of SDRAM modules within Sung's stacking architecture.

4. Relief Requested

  • Petitioner requests institution of an IPR and cancellation of claims 1, 2, 11, and 12 of the ’243 patent as unpatentable.