PTAB

IPR2018-01720

Samsung Electronics Co., Ltd. v. BiTMICRO, LLC

Log In

1. Case Identification

2. Patent Overview

  • Title: Stacked Module with Serial Chain Routing
  • Brief Description: The ’243 patent describes methods for creating stacked multi-chip modules (MCMs) to increase memory density and miniaturize storage devices. The challenged claims are directed to a system with at least two serial signal chains and control circuitry that can selectively create a routing path between them within an end module, enabling functions like JTAG boundary scan testing across the stack.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sato - Claims 1, 2, 11, and 12 are obvious over Sato.

  • Prior Art Relied Upon: Sato (International Publication No. WO 2004/072667).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sato discloses every element of the challenged claims. Sato teaches a stack of memory modules that perform a JTAG boundary scan using a "daisy chain" configuration. This daisy chain, carrying TDI (Test Data Input) and TDO (Test Data Output) signals, constitutes the claimed "first serial chain route." Sato further discloses a separate TDO2 signal path, which functions as the "second serial chain route." In the uppermost "end module" where there is no subsequent module to receive the TDO signal, Sato discloses control circuitry (a tri-state buffer and comparison logic) that enables a "routing path" to connect the TDI input (first chain) to the TDO2 output (second chain). This control circuit is activated in response to a control signal indicating its position as the end module, thus meeting the limitations of independent claim 1.
    • Key Aspects: Petitioner contended that Sato's architecture for handling JTAG signals in the top-most chip of a stack is functionally identical to the claimed invention.

Ground 2: Obviousness over Sato in view of Gaynes - Claims 1, 2, 11, and 12 are obvious over Sato in view of Gaynes.

  • Prior Art Relied Upon: Sato (WO 2004/072667) and Gaynes (Patent 6,236,115).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative, anticipating that the Patent Owner might argue the claims require specific physical structures for ports, such as the ball-and-pad connections mentioned in the ’243 patent's specification. While Sato discloses the necessary functional system, Gaynes was introduced to explicitly teach the implementation details for these connections. Gaynes discloses forming penetrating electrodes (through-silicon vias or "TSVs") in connection with pads and solder balls to create robust chip-to-chip interconnections in a stacked module.
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) implementing the JTAG system of Sato would have been motivated to look to known prior art like Gaynes for well-established methods of fabricating the physical interconnections. Gaynes provided an advantageous and common method for creating the vertical connections (TSVs, balls, pads) needed for Sato's stacked architecture, offering benefits like enhanced durability and improved electrical performance.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in this combination because both references address the same technical problem of interconnecting stacked semiconductor chips. Applying Gaynes's specific pad-and-ball TSV structure to implement Sato's functional penetrating electrodes would have been a predictable combination of known elements for their intended purpose.

Ground 3: Obviousness over Sung - Claims 1, 2, 11, and 12 are obvious over Sung.

  • Prior Art Relied Upon: Sung (Application # 2003/0178228).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Sung, by itself, renders the claims obvious by teaching an analogous architecture. Sung discloses a three-dimensional stack of integrated circuits with an "inter-die scan chain" that functions as the claimed "first serial chain route." Sung also describes a "broadcasting circuit" for data conveyance, which serves as the "second serial chain route." Critically, Sung discloses control circuitry (a "die identifier circuit" and a "tristate buffer") located in the bottom "end module." This control circuit enables a routing path between the scan chain and the broadcasting circuit. The circuit is enabled in response to a control signal (a ground signal from an adjacent module, or a pull-up voltage when no module is stacked below), which demonstrates the claimed functionality of enabling the path in an end module based on a signal from another module.
    • Key Aspects: Petitioner highlighted that Sung’s control logic, which determines whether a module is at the bottom of the stack and reroutes signals accordingly, operates in the same manner as the control circuit in the ’243 patent.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on Sato in view of Eide (Patent 5,612,570) to teach mounting chips on a PCB substrate, and Sung in view of Matsui (Application # 2004/0257847) to explicitly teach the use of SDRAM modules. These grounds relied on similar rationales of combining known elements for their predictable functions.

4. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1, 2, 11, and 12 of Patent 7,826,243 as unpatentable.