LG Innotek Co Ltd v. Seoul Semiconductor Co Ltd

1. Case Identification

• Case #: IPR2019-01154
• Patent #: 9,293,664
• Filed: June 11, 2019
• Petitioner(s): LG Innotek Co. Ltd.
• Challenged Claims: 1-19

2. Patent Overview

• Title: Wafer-Level Light Emitting Diode Package and Method of Fabricating the Same
• Brief Description: The ’664 patent relates to a light-emitting diode (LED) package that includes a semiconductor stack with contact holes exposing a lower semiconductor layer. A key feature is a protective insulation layer covering the sidewall of the stack, where the insulation layer includes sub-layers with different indices of refraction.

3. Grounds for Unpatentability

Ground 1A: Anticipation by Illek - Claims 1-6, 8, 9, 11, and 12 are anticipated by Illek.

• Prior Art Relied Upon: Illek (Application # 2010/0117111).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Illek, which discloses an optoelectronic component, teaches every limitation of the challenged claims. Illek describes an LED with a semiconductor body (first and second conductive layers with an active region), a plurality of openings (contact holes) exposing the first layer, and first and second electrode pads. Critically, Illek’s protective layer includes a "mirror layer 14" described as a multilayer dielectric structure with layers having different refractive indices arranged alternatingly, directly corresponding to the key limitation of claim 1 requiring insulation layers with different indices of refraction.
  • Key Aspects: The argument centered on Illek’s mirror layer 14, composed of multiple dielectric layers, explicitly teaching the novel feature identified by the Examiner during prosecution of the ’664 patent.

Ground 1C: Obviousness over Illek and Begemann - Claims 7 and 19 are obvious over Illek in view of Begemann.

• Prior Art Relied Upon: Illek (Application # 2010/0117111) and Begemann (Application # 2003/0021113).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed claims 7 and 19, which add the limitation of a metal-core printed circuit board (MC-PCB). Petitioner asserted that while Illek teaches mounting its LED package on a generic circuit board, it does not specify the type. Begemann explicitly discloses using an MC-PCB for LED applications to provide high heat conduction and dissipate the excess heat generated by LED chips.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Illek's LED package with Begemann's MC-PCB to solve the well-known problem of thermal management in LEDs. Since both references are in the same field and address mounting LEDs on circuit boards, a POSITA would have recognized that the superior heat dissipation of an MC-PCB would predictably improve the performance and reliability of Illek's device.
  • Expectation of Success: The combination was presented as a routine and conventional design choice, as using MC-PCBs for thermal management was a popular and well-understood technique at the time, yielding predictable results.

Ground 2A: Obviousness over Donofrio and Sano - Claims 1-19 are obvious over Donofrio in view of Sano.

• Prior Art Relied Upon: Donofrio (Application # 2009/0283787) and Sano (JP Publication # 2009-88299).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued Donofrio discloses an LED structure with nearly all claimed features, including a semiconductor stack, contact vias, and an insulating layer comprising multiple sublayers (oxide and nitride) to form a distributed Bragg reflector, which inherently have different refractive indices. For any perceived deficiency in Donofrio's disclosure of the insulating layer covering the sidewalls of both semiconductor layers, Sano was introduced. Petitioner contended that a POSITA would understand that the via etching process described in Donofrio would slightly "over-etch" into the lower semiconductor layer to ensure a good electrical contact, a standard manufacturing practice confirmed by Sano. This over-etching would create a sidewall in the lower layer that would subsequently be covered by the insulating layer, thus meeting the claim limitation. Sano also supplied teachings for the wavelength converter.
  • Motivation to Combine: A POSITA would have looked to a reference like Sano to understand the practical results of the manufacturing processes described in Donofrio. The motivation was to implement Donofrio's design using known, reliable fabrication techniques, such as the slight over-etching taught by Sano, to ensure proper device function (i.e., reliable electrical contact).
  • Expectation of Success: Combining the teachings was argued to be a straightforward application of conventional semiconductor manufacturing principles to achieve a predictable outcome—a functioning LED with reliable contacts and insulated sidewalls.

• Additional Grounds: Petitioner asserted an alternative obviousness challenge for claims 1-6 and 8-18 based solely on Illek (Ground 1B) and an additional obviousness challenge for claim 19 based on Donofrio, Sano, and Begemann (Ground 2B).

4. Key Technical Contentions (Beyond Claim Construction)

• Over-Etching as an Inherent Process Step: A central technical argument, particularly for the Donofrio-based grounds, was that a POSITA would have inherently understood that etching a via through multiple semiconductor layers to expose an underlying layer would require a slight over-etch into that bottom layer. This was presented not as a modification but as a necessary and common step in semiconductor manufacturing to ensure a clean and reliable electrical connection, which Donofrio’s idealized illustration did not explicitly show.
• Scope of "Protective Insulation Layer": Petitioner contended that insulation layers deposited on a semiconductor stack inherently provide protection by passivating the underlying material and preventing short circuits. The argument suggested that requiring additional "protection from an external environment" would be an improper narrowing of the claim term, but even if it were required, the prior art insulation layers would meet that function.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. § 325(d), acknowledging that the primary references (Illek and Donofrio) were cited in an Information Disclosure Statement (IDS) during the original prosecution of the ’664 patent. However, Petitioner emphasized that the Patent Office never substantively considered or applied these references in any rejection. Citing PTAB precedent, Petitioner argued that mere citation in an IDS without any evidence of substantive review by the examiner is insufficient to justify discretionary denial, especially where the prior art plainly teaches the features that led to allowance.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-19 of Patent 9,293,664 as unpatentable.