LG Innotek Co. Ltd. v. Seoul Semiconductor Co., Ltd.

1. Case Identification

• Case #: IPR2019-01154
• Patent #: 9,293,664
• Filed: June 11, 2019
• Petitioner(s): LG Innotek Co. Ltd.
• Patent Owner(s): Seo, et al.
• Challenged Claims: 1-19

2. Patent Overview

• Title: WAFER-LEVEL LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME
• Brief Description: The ’664 patent relates to a light-emitting diode (LED) package that includes a semiconductor stack with first and second conductive layers, an active layer, and contact holes for electrical connection. A key feature is a protective insulation layer covering a sidewall of the semiconductor stack, where this protective layer includes multiple insulation layers having different indices of refraction from each other.

3. Grounds for Unpatentability

Ground 1: Claims 1-6, 8-9, and 11-12 are anticipated by Illek; Claims 10 and 13-18 are obvious over Illek

• Prior Art Relied Upon: Illek (Application # 2010/0117111).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Illek discloses every element of the challenged claims. Illek teaches an LED component with a semiconductor body (first/second conductive regions, active region), a plurality of openings (contact holes) to contact the lower conductive region, and first/second electrode pads. Critically, Illek’s protective layer includes a “mirror layer 14,” described as a multilayer structure of dielectric layers with different, alternating refractive indices, which directly teaches the key limitation of the ’664 patent. For claims argued as obvious, Petitioner contended that features like specific electrode pad sizing (claim 10) were a matter of routine design choice for a POSITA seeking to optimize flip-chip mounting and heat dissipation, which were known objectives in the art.
  • Motivation to Combine (for §103 grounds): For the obviousness arguments, the motivation was presented as simple design choice. A POSITA would have recognized that maximizing the area of electrode pads, as recited in claim 10, was a well-known technique to improve mounting tolerance and heat dissipation in flip-chip LEDs.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in applying these routine design modifications to Illek’s device to achieve predictable results.

Ground 2: Claims 7 and 19 are obvious over Illek in view of Begemann

• Prior Art Relied Upon: Illek (Application # 2010/0117111) and Begemann (Application # 2003/0021113).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the teachings of Illek by adding Begemann. While Illek teaches mounting an LED component on a generic circuit board, dependent claim 7 of the ’664 patent specifically requires a metal-core printed circuit board (MC-PCB). Petitioner asserted that Begemann explicitly teaches using an MC-PCB for LED applications specifically because of its high heat conduction and dissipation properties.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Illek’s LED device with Begemann’s MC-PCB to solve the well-known problem of heat generation in LEDs. Since Illek recognized the need to reduce internal temperatures and Begemann taught the MC-PCB as a solution for superior heat transfer, the combination was a straightforward application of a known solution to a known problem.
  • Expectation of Success (for §103 grounds): The combination would predictably result in an LED module with improved thermal performance, as both references operated in the same technical field and addressed compatible problems.

Ground 3: Claims 1-19 are obvious over Donofrio in view of Sano

• Prior Art Relied Upon: Donofrio (Application # 2009/0283787) and Sano (JP Publication JP 2009-88299).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Donofrio discloses a similar flip-chip LED structure with a semiconductor stack, vias (contact holes), and a multi-sublayer insulating layer that functions as a distributed Bragg reflector (implying different refractive indices). However, Donofrio’s diagrams did not explicitly show the protective insulation layer covering the sidewalls of both the first and second conductive layers. Petitioner introduced Sano, which teaches a similar etching process, to show that a slight, expected over-etch into the first conductive layer is a practical necessity to ensure good electrical contact. This over-etching would result in the protective insulation layer covering the sidewalls of both layers, as claimed.
  • Motivation to Combine (for §103 grounds): A POSITA would incorporate the practical etching technique from Sano into the process for making Donofrio’s device to improve manufacturing reliability. The goal was to ensure a reliable electrical connection, and over-etching as taught by Sano was a conventional method to achieve this, avoiding incomplete etching that would lead to poor contact.
  • Expectation of Success (for §103 grounds): A POSITA would expect that applying a common over-etching technique to Donofrio's fabrication process would predictably result in a functional device with more reliable electrical contacts.

• Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 19 based on the combination of Donofrio, Sano, and Begemann, arguing that Begemann's teaching of mounting multiple LED chips on an MC-PCB was a routine and conventional design choice.

4. Key Technical Contentions (Beyond Claim Construction)

• Practicality of Semiconductor Etching: A central technical argument, particularly for the Donofrio/Sano ground, was that a POSITA would understand that the idealized diagrams in a patent like Donofrio do not reflect manufacturing realities. Petitioner contended that stopping a multi-layer etch process perfectly at the boundary between two semiconductor layers is highly unlikely. Therefore, a POSITA would have inherently understood the need for a slight "over-etch" to ensure complete exposure of the underlying layer for electrical contact, which in turn would cause the subsequently applied protective layer to cover the sidewalls of both semiconductor layers.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §325(d) would be inappropriate. Although the primary references (Illek and Donofrio) were cited in an Information Disclosure Statement (IDS) during the original prosecution of the ’664 patent, Petitioner asserted there was no evidence they were substantively considered by the Examiner. The prosecution history shows no rejections were ever made, and the Examiner’s reasons for allowance did not mention or analyze these references, indicating they were only "cursorily considered."

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-19 of the ’664 patent as unpatentable.