Intel Corp v. Tela Innovations Inc

1. Case Identification

• Case #: IPR2019-01520
• Patent #: 10,186,523
• Filed: August 19, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): Tela Innovations, Inc.
• Challenged Claims: 1, 2, 8-12, 25-26

2. Patent Overview

• Title: Semiconductor Device with Regular Circuit Layout
• Brief Description: The ’523 patent relates to a semiconductor integrated circuit layout using a "dynamic array" architecture. This architecture employs linear-shaped features, such as gate electrodes and metal interconnects, arranged in regular, grid-based patterns to improve manufacturability and device yield.

3. Grounds for Unpatentability

Ground 1: Obviousness over Yano, Kitabayashi, and Ikoma - Claims 1, 2, 8-12, and 25-26 are obvious over Yano in view of Kitabayashi and Ikoma.

• Prior Art Relied Upon: Yano (Patent 7,538,368), Kitabayashi (Patent 7,200,831), and Ikoma (Patent 7,279,727).
• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that the combination of Yano, Kitabayashi, and Ikoma rendered the challenged claims obvious. Yano was asserted to provide the foundational regular gate-level layout, including linear, rectangular gate electrode features for multiple transistors of different types, all arranged with uniform spacing that establishes a gate grid. Yano’s layout, however, did not fully detail the necessary metal wiring layers.

  • A POSITA would look to a reference like Kitabayashi to provide the multi-level metal interconnect stack needed to complete Yano's circuit. Kitabayashi taught an orthogonal, multi-layer interconnect system where wiring traces in each layer are linear, regularly spaced, and run in a common direction, which is orthogonal to the direction of traces in adjacent layers. This system, including the claimed first-metal, second-metal, and third-metal layers, would be placed over Yano's gate structures. Kitabayashi’s use of dummy conductors ensures that each gridline has a metal structure, as claimed.

  • To connect these metal layers to Yano's gates, a POSITA would use the method taught by Ikoma. Ikoma addressed the known problem of gate shape distortion caused by contact landing pads by teaching the use of oversized, rectangular gate contacts that overlap both edges of the underlying gate. This technique allows the gate to remain a simple, linear rectangle, preserving the regularity central to Yano's invention. Petitioner mapped this combination to the limitations of claim 1, including the gate grid, multiple transistor types, at least six gate contacts, and a first-metal layer with at least eight gridlines.

  • For the dependent claims, Petitioner contended Kitabayashi's multi-layer stack inherently taught the second-metal layer (claim 2) and third-metal layer (claim 10). The required pitch of these metal grids and their alignment with the diffusion contact grid (claim 8) were argued to be obvious implementations to facilitate routing and ensure consistent manufacturability, a principle taught by all three references.

  • Motivation to Combine: A POSITA would combine these references for complementary reasons. Yano’s gate layout is incomplete without the wiring taught by Kitabayashi; Kitabayashi’s philosophy of regular, gridded wiring to improve yield directly mirrors and complements Yano’s gate-level approach, making the combination logical for achieving end-to-end manufacturability. Furthermore, a POSITA implementing Yano's design would be motivated to use Ikoma's overlapping contact method to solve the well-known problem of gate distortion during fabrication, thereby preserving the very regularity and process control that Yano sought to achieve. The combination addressed known problems using known solutions from the same field.

  • Expectation of Success: A POSITA would have had a reasonable expectation of success in combining the references. The teachings were complementary, addressing distinct but related aspects of integrated circuit design (gate layout, interconnect wiring, and contact formation) using conventional and compatible planar CMOS technologies. The integration was presented as a matter of applying known design principles, posing no technical risks and leading to the predictable benefits of improved layout uniformity and manufacturability.

4. Key Claim Construction Positions

• gate electrode feature(s): Petitioner proposed a structural definition: a “linear-shaped feature comprising a gate(s) of a transistor(s) or a dummy gate.” This construction focused on the physical shape and function within the layout, which Petitioner argued was clearly disclosed in the prior art figures showing linear, rectangular polysilicon structures.
• gate contact structure(s): Petitioner proposed this term means “conductive structure(s) in a gate contact layer above and separate from the gate layer and below and separate from interconnect layers.” This emphasizes the structure’s position within a distinct layer of the semiconductor stack, a configuration Petitioner contended was explicitly shown in references like Ikoma.
• Petitioner argued that the invalidity grounds apply regardless of which party's construction is adopted, as the prior art discloses the claimed features under any reasonable interpretation.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §314(a) in view of parallel proceedings in the Northern District of California and the International Trade Commission. Petitioner asserted that PTAB precedent does not treat an ITC investigation as a first-filed action for discretionary denial purposes. It further argued that denial was improper because the challenged claims of the ’523 patent contained unique limitations not present in other patents from the same family that were subject to other IPR petitions.

6. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 2, 8-12, and 25-26 of Patent 10,186,523 as unpatentable.