PTAB

IPR2020-01007

Micron Technology Inc v. Godo Kaisha IP Bridge 1

Key Events

Petition

petition

Title: Semiconductor Device
Brief Description: The ’041 patent relates to a semiconductor device, such as a DRAM, designed to prevent copper atoms from wiring interconnects from diffusing into the device's memory storage portion. The patent discloses using a "copper diffusion blocking means," such as a silicon nitride "ceiling film" over the memory portion and a "vertical wall" alongside it, to create a protective barrier.

Prior Art Relied Upon: Liang (Patent 6,368,952).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Liang teaches a semiconductor memory device that addresses the same problem of copper diffusion. Liang discloses a memory storage portion (transistor T2) that is fully encapsulated by diffusion barrier layers structurally indistinguishable from those claimed in the ’041 patent. Specifically, Liang's "blanket capping diffusion barrier dielectric layer 26" is the claimed "ceiling film," and its "patterned diffusion barrier dielectric layers 24a and 24b" form the claimed "vertical wall." Both structures are taught to be made of materials like silicon nitride to prevent copper diffusion.
- Motivation to Combine (for §103 grounds): As a single-reference ground, Petitioner contended that Liang itself provides all necessary elements and motivation. Liang’s explicit purpose was to create a "diffusion inhibited dielectric structure for a diffusion enhanced conductor layer," directly teaching the solution claimed in the ’041 patent.
- Expectation of Success (for §103 grounds): Petitioner asserted success was expected because Liang's disclosed structure was specifically designed to prevent copper diffusion into its memory circuit, achieving the exact function of the challenged claims.

Prior Art Relied Upon: Liang (Patent 6,368,952) and El-Kareh (a May 1997 article titled "The Evolution of DRAM Cell Technology").
Core Argument for this Ground:
- Prior Art Mapping: This ground builds on the teachings of Liang by addressing the limitations of claims 13 and 14, which require the memory storage portion to be for "accumulating and releasing charges" (i.e., a capacitor). While Liang primarily discusses a transistor-based memory, it explicitly discloses that a capacitor can be used as an alternative storage element. El-Kareh provides detailed context on the structure and function of capacitor-based DRAM cells.
- Motivation to Combine (for §103 grounds): Petitioner argued that El-Kareh established that capacitor-based DRAM was the predominant memory technology at the time of the invention. A person of ordinary skill in the art (POSITA) would combine Liang's diffusion-blocking structure with the capacitor-based memory cell described by El-Kareh to apply Liang’s solution to the most commercially relevant form of memory. Protecting DRAM capacitors from copper diffusion was a known and important goal.
- Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as Liang already taught its invention could be used with capacitors, and El-Kareh described the standard implementation of such memory cells.

Prior Art Relied Upon: Kishii (JP H5-198769A) and Ryan (a July 1995 article titled "The Evolution of Interconnection Technology at IBM").
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Kishii discloses a DRAM device with a stacked capacitor memory element completely surrounded by a thick "protective film" (film 28) made of silicon nitride (Si₃N₄). While Kishii does not explicitly state the film is for blocking copper, Petitioner argued its structure and material (a known barrier material) inherently perform the claimed function. Ryan teaches that multilevel interconnects in DRAMs are advantageously made from copper.
- Motivation to Combine (for §103 grounds): A POSITA would be motivated to apply Ryan's teaching of using superior, low-resistivity copper interconnects to Kishii’s DRAM device. Kishii explicitly states its device is intended for use with "multilayer interconnects," and Ryan teaches that copper was the preferred material for such interconnects to improve device speed and reliability.
- Expectation of Success (for §103 grounds): Success would be expected because Kishii's thick silicon nitride protective film, which already surrounded the memory capacitor, would be immediately recognized by a POSITA as a reliable barrier against diffusion from the copper interconnects taught by Ryan, mitigating any potential diffusion concerns.

"apart from said memory storage portion" (Claim 1): Petitioner proposed this term be construed to mean "not part of" or "not a component of the memory storage portion." This construction was argued to be critical to rebut the Patent Owner's anticipated position that a specific "spacing" is required between the wiring and memory portions, a limitation Petitioner contended is not supported by the claim language and is not met by the prior art in all instances.
"copper-diffusion blocking means" (Claim 1): Petitioner argued this is a means-plus-function term under 35 U.S.C. §112, ¶ 6.
- Function: "blocking copper diffusion from said wiring portion toward said memory storage portion."
- Corresponding Structure: a "ceiling film or a vertical wall," as described in the ’041 patent's specification. This construction limits the claim scope to the specific structures disclosed, which Petitioner asserted were fully taught by the cited prior art.

Petitioner argued that the Board should not exercise its discretion to deny institution under the Fintiv factors. The core arguments were that the petition was filed expeditiously (less than three months after Petitioner was sued), the co-pending district court litigation was in its earliest stages with no trial date set and minimal investment from the parties, and the strong merits of the petition favored institution to promote overall system efficiency and integrity.

Petitioner requested institution of an inter partes review and cancellation of claims 1-17 of Patent 6,424,041 as unpatentable.