Micron Technology Inc v. Godo Kaisha IP Bridge 1

1. Case Identification

• Case #: IPR2020-01008
• Patent #: 6,445,047
• Filed: June 4, 2020
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Godo Kaisha IP Bridge 1
• Challenged Claims: 1-4

2. Patent Overview

• Title: Semiconductor Device and Method for Fabricating the Same
• Brief Description: The ’047 patent discloses a semiconductor device, such as a DRAM, that integrates two different types of surface-channel-type MOSFETs. The first type uses a polysilicon gate electrode for logic circuits, while the second type uses a refractory metal gate electrode for memory cells to achieve a higher threshold voltage.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1, 2, and 4 by Yanagawa

• Prior Art Relied Upon: Yanagawa (A 1-µm Mo-Poly 64-kbit MOS RAM, IEEE Transaction on Electron Devices, Aug. 1980).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Yanagawa, which describes a 64-kbit MOS RAM using molybdenum and polysilicon (Mo-poly) technology, discloses every limitation of claims 1, 2, and 4. Yanagawa’s “Si-gate” transistors used in the peripheral (logic) circuitry correspond to the claimed "first MOSFET," and its “Mo-gate” transistors used in the memory cells correspond to the claimed "second MOSFET." Specifically, Yanagawa was alleged to disclose a first MOSFET with a polysilicon gate, a 0.5V threshold voltage, a 30 nm gate oxide, and a channel dopant concentration of 5.9 x 10¹¹/cm². It also disclosed a second MOSFET with a refractory metal (molybdenum) gate, a higher 1.3V threshold voltage, a thicker 40 nm gate oxide, and a lower channel dopant concentration (no implant), satisfying all limitations of the challenged claims.

Ground 2: Obviousness of Claim 3 over Yanagawa in view of An

• Prior Art Relied Upon: Yanagawa (IEEE Transaction on Electron Devices, Aug. 1980) and An (Patent 6,165,849).
• Core Argument for this Ground:
  • Prior Art Mapping: Claim 3 requires that the second MOSFET (the higher threshold, thicker gate oxide transistor) controls power supplied to the logic circuit block. Petitioner contended that while Yanagawa places this transistor in the memory cell, it would have been obvious to use it for the device’s input/output (I/O) circuitry, which controls power for the entire device, including the logic block.
  • Motivation to Combine: A POSITA would combine these references because An expressly taught that it was conventional to use transistors with thicker gate oxides for I/O circuits to withstand higher external voltages and protect against electrostatic discharge (ESD). Since Yanagawa already provided two transistor types with different gate oxide thicknesses (30 nm and 40 nm), a POSITA would have been motivated by An to use Yanagawa’s existing, more robust Mo-gate transistor (with the 40 nm oxide) for the I/O power control function.
  • Expectation of Success: Petitioner argued a POSITA would have a high expectation of success because the combination involved using a transistor already present in Yanagawa’s device for a well-known purpose (I/O power control). The modification would only require fabricating the Mo-gate transistor in the I/O region in addition to the memory region, a minor change to the mask pattern.

Ground 3: Obviousness of Claims 1, 2, and 4 over Houston

• Prior Art Relied Upon: Houston (Patent 6,424,016).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Houston discloses a DRAM with two transistor types that render the claims obvious. Houston’s P-FET peripheral logic transistors correspond to the "first MOSFET," and its N-FET pass transistors in the memory array correspond to the "second MOSFET." Houston taught using a refractory metal gate (e.g., tungsten) for the pass transistors to achieve a higher threshold voltage (1.2V) than the peripheral transistors (-0.5V). Houston also disclosed different dopant concentrations for the two transistor types.
  • Motivation to Combine (Rationale for Obviousness): For the limitation requiring the second transistor’s gate insulating film to be thicker, Petitioner argued this was an obvious design choice. Houston noted that while it is "usual" to use the same gate oxide thickness for cost reasons, peripheral logic transistors are generally designed with lower threshold voltage (Vt) for higher performance. A POSITA knew that a standard way to optimize performance for lower-Vt logic transistors was to design them with a thinner gate oxide. Therefore, it would have been an obvious modification to Houston’s design to make the logic transistors with a thinner gate oxide than the pass transistors to optimize performance.
  • Expectation of Success: A POSITA would have a high expectation of success, as Houston itself recognized the performance-cost tradeoff. Furthermore, well-known prior art processes were available to fabricate transistors with different gate insulating film thicknesses on the same chip.
• Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1, 2, and 4 are obvious over Yanagawa and that claim 3 is obvious over Houston in view of An, relying on similar technical rationales and design modification theories.

4. Key Claim Construction Positions

• “Surface-channel-type MOSFET” (Claims 1-4): Petitioner proposed that this term should be construed to mean “a MOSFET in which the channel forms near the top surface of the semiconductor substrate.” This construction was based on the term’s plain meaning and its contrast with “buried-channel” devices, where carriers propagate slightly under the semiconductor surface. Petitioner argued this construction was critical because both Yanagawa and Houston disclose transistors where channel doping creates a surface channel, not a buried channel.
• “Logic Circuit Block” / “Memory Cell Block” (Claims 3-4): Petitioner argued that an express construction was unnecessary but, for clarity, proposed that “logic circuit block” includes the peripheral logic of a RAM (e.g., decoders, buffers) and “memory cell block” includes the memory core (e.g., access transistors, storage elements).

5. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise its discretion to deny institution.
• Against §325(d) Denial: The petition presented prior art (Yanagawa and Houston) that was substantially different from the art considered during prosecution. The examiner was not aware of any prior art that disclosed a transistor with a refractory metal gate formed directly on the gate insulating film, a key feature taught by both Yanagawa and Houston.
• Against §314(a) Denial (Fintiv Factors): Petitioner argued the Fintiv factors weighed in favor of institution. The petition was filed expeditiously (less than three months after being sued), and at the time of filing, no significant parallel litigation activity had occurred, no trial date was set, and no infringement contentions had been served. Petitioner contended that the strong merits of the petition served the interest of system efficiency and integrity.

6. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-4 of the ’047 patent as unpatentable.