PTAB

IPR2020-01008

Micron Technology, Inc. v. Godo Kaisha IP Bridge 1

Title: Semiconductor Device and Method for Fabricating the Same
Brief Description: The ’047 patent describes a semiconductor device using two distinct types of surface-channel-type MOSFETs on a single chip. A first type with a polysilicon gate is used in a logic circuit block, while a second type with a refractory metal gate, higher threshold voltage, lower dopant concentration, and thicker gate insulating film is used in a memory cell block.

Prior Art Relied Upon: Yanagawa (A 1-µm Mo-Poly 64-kbit MOS RAM, IEEE (1980)).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Yanagawa, a 1980 technical paper on DRAM, discloses every limitation of claims 1, 2, and 4. Yanagawa was asserted to teach a "double-gate" technology using two types of MOSFETs: "Si-gate" (polysilicon) transistors for "peripheral circuitry" (the claimed logic circuit block) and "Mo-gate" (molybdenum, a refractory metal) transistors for "memory cells" (the claimed memory cell block). Petitioner mapped Yanagawa's "Si-gate" transistor to the claimed "first MOSFET" and the "Mo-gate" transistor to the "second MOSFET." Based on Yanagawa's Table 1, Petitioner contended the Mo-gate transistor has a higher threshold voltage (1.3 V vs. 0.5 V), a thicker gate oxide (40 nm vs. 30 nm), and a lower channel dopant concentration (no implant vs. a B+ dose), thereby anticipating the limitations of the challenged claims.

Prior Art Relied Upon: Yanagawa (A 1-µm Mo-Poly 64-kbit MOS RAM, IEEE (1980)), An (Patent 6,165,849).
Core Argument for this Ground:
- Prior Art Mapping: This ground addressed claim 3, which requires the second, more robust MOSFET to control power supplied to the logic circuit. Petitioner argued that An teaches the known practice of using high-voltage transistors with thicker gate oxides in input/output (I/O) circuits to protect against electrostatic discharge (ESD) and handle higher external voltages.
- Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings by using Yanagawa's more robust Mo-gate transistors (which have a thicker gate oxide and higher threshold voltage) for the I/O circuitry. This circuitry receives and controls the external power supply for the entire chip, including the logic block, to improve reliability and ESD protection as taught by An.
- Expectation of Success: A POSITA would have a high expectation of success, as Yanagawa already demonstrated the successful fabrication of both transistor types on a single chip. Applying the Mo-gate transistor to the I/O portion would be a predictable design choice involving only minor modifications to the fabrication mask pattern.

Prior Art Relied Upon: Houston (Patent 6,424,016).
Core Argument for this Ground:
- Prior Art Mapping: As an alternative ground, Petitioner argued Houston renders the claims obvious. Houston described a DRAM with transistors in a "periphery area" (logic block) and an "array area" (memory block). Petitioner mapped Houston's P-FET peripheral transistors (with polysilicon gates) to the "first MOSFET." Houston was argued to teach that N-FET pass transistors in the memory array can use a refractory metal gate (e.g., tungsten) to achieve a higher threshold voltage for lower leakage, corresponding to the "second MOSFET." Petitioner further asserted Houston shows the pass transistors have a lower channel dopant concentration and that it would have been obvious to a POSITA to make the logic transistor's gate oxide thinner than the pass transistor's oxide to optimize performance, a known design trade-off.
Additional Grounds: Petitioner asserted additional obviousness challenges, including a challenge to claim 3 over Houston in view of An and an alternative obviousness challenge to claims 1, 2, and 4 over Yanagawa in view of a POSITA's knowledge, relying on similar technical rationales and motivations to combine.

"Surface-channel-type MOSFET": Petitioner proposed this term means "a MOSFET in which the channel forms near the top surface of the semiconductor substrate." This construction was used to distinguish from "buried-channel" devices and to argue that the transistors described in both Yanagawa and Houston, which use opposite-type channel doping relative to the substrate, are of the claimed type.
"Logic Circuit Block" / "Memory Cell Block": Petitioner argued these terms should be understood to respectively encompass the peripheral logic circuitry (e.g., decoders, buffers) and the memory core (which includes access transistors) of a DRAM. This was essential for mapping terms like "peripheral circuitry" from Yanagawa and "periphery area" from Houston to the language of the claims.

Petitioner argued against discretionary denial under 35 U.S.C. §325(d), asserting that the primary prior art (Yanagawa and Houston) was not considered during prosecution and is substantially different from the art of record. Petitioner contended that this new art teaches the key feature of a refractory metal gate formed directly on the gate insulating film—a feature the patent applicant allegedly used to overcome rejections during prosecution.
Petitioner also argued against discretionary denial under Fintiv factors (§314(a)). It contended that the petition was filed expeditiously (less than three months after being sued) and that the co-pending district court litigation was in its earliest stages, with no trial date set and minimal investment from either party. Petitioner asserted these factors weigh heavily in favor of institution to promote system efficiency and integrity.

Petitioner requests institution of an inter partes review and cancellation of claims 1-4 of Patent 6,445,047 as unpatentable.