PTAB

IPR2020-01009

Micron Technology, Inc. v. Godo Kaisha IP Bridge

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1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with DRAM Inside
  • Brief Description: The ’320 patent discloses a semiconductor device, specifically a DRAM sense amplifier, designed to suppress variations in characteristics between adjacent sense amplifiers. The design involves arranging transistor gates in a linear, parallel formation relative to each other and to the bit lines, and can be used in embedded DRAM (EDRAM) applications.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claim 1 over Hidaka, Luk, and Takemura

  • Prior Art Relied Upon: Hidaka (Patent 6,018,172), Luk (Patent 5,883,814), and Takemura (Patent 6,477,100).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hidaka discloses a DRAM with CMOS sense amplifiers where the gate electrodes are arranged in a linear fashion, parallel to each other and to the DRAM bit lines, satisfying the core structural limitations of claim 1. To meet the "co-resident" DRAM and high-speed logic limitation, Petitioner pointed to Luk, which teaches the known benefits and methods of embedding a DRAM system with a separate logic processor on a single semiconductor chip. Finally, to meet the requirement for "shallow trench isolation (STI)," Petitioner relied on Takemura, which expressly teaches using STI (termed "shallow groove isolation") to isolate adjacent sense amplifier transistors in a similar DRAM architecture.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine Luk with Hidaka to achieve the well-understood advantages of embedded DRAM, including higher performance, lower power consumption, and greater design flexibility, as explicitly detailed by Luk. A POSITA would also have been motivated to substitute Hidaka’s disclosed LOCOS isolation with the STI taught by Takemura, as STI was a known and superior alternative that eliminated the "bird's beak" encroachment problem of LOCOS and enabled more compact device layouts, a critical goal in memory design.
    • Expectation of Success: Petitioner asserted a high expectation of success, arguing that embedding a DRAM (per Luk) was a known design variation and substituting one known isolation method (LOCOS) for another, more advanced one (STI per Takemura) was a routine and predictable design choice to achieve known benefits.

Ground 2: Obviousness of Claims 4-6 over Hidaka and Luk

  • Prior Art Relied Upon: Hidaka (Patent 6,018,172) and Luk (Patent 5,883,814).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targets claims requiring isolation via a "field shield electrode" instead of STI. Petitioner asserted that the core sense amplifier structure and the co-resident logic limitations were taught by Hidaka and Luk, respectively, for the same reasons as in Ground 1. For the key isolation element, Petitioner argued that Hidaka itself explicitly teaches using a "field shield electrode" as a direct alternative to LOCOS isolation for separating adjacent transistors. Hidaka’s figures show this electrode positioned between active regions, and Petitioner argued this structure would be parallel to the gate electrodes as required by claim 4. For dependent claim 6, Petitioner argued Hidaka II (a related patent) confirms that such field shield electrodes are operated by applying a ground or negative potential.
    • Motivation to Combine: The motivation to combine Hidaka and Luk was the same as in Ground 1: to obtain the benefits of an embedded DRAM system. The motivation to use a field shield electrode was provided directly by Hidaka, which presents it as a disclosed, available option for transistor isolation. A POSITA would thus have been motivated to select this known isolation technique to achieve a more compact and reliable design compared to LOCOS.
    • Expectation of Success: A POSITA would have had a high expectation of success because Hidaka expressly teaches both the sense amplifier layout and the use of field shield electrodes for isolation, making it a straightforward application of teachings within a single reference, combined with the well-known practice of creating embedded DRAMs taught by Luk.

Ground 3: Obviousness of Claim 1 over Aoyama, Luk, and Takemura

  • Prior Art Relied Upon: Aoyama (Patent 4,730,280), Luk (Patent 5,883,814), and Takemura (Patent 6,477,100).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative to Ground 1, substituting Aoyama for Hidaka as the base reference. Petitioner argued that Aoyama teaches a DRAM device with CMOS sense amplifiers having gate electrodes arranged parallel to each other and to the bit lines, thus disclosing the fundamental sense amplifier structure. As in Ground 1, Luk was cited for the teaching of embedding this DRAM architecture with co-resident logic, and Takemura was cited for the teaching of using STI to isolate adjacent sense amplifiers.
    • Motivation to Combine: The motivation was analogous to Ground 1. A POSITA would be motivated to apply Luk's teachings to Aoyama’s memory design to gain the performance and efficiency benefits of a single-chip embedded system. Likewise, a POSITA would be motivated to use the STI taught by Takemura as a modern, space-efficient isolation method for the sense amplifiers in Aoyama's design, which was a routine engineering choice to improve device density.
    • Expectation of Success: Petitioner argued success would have been reasonably expected because Aoyama taught a conventional sense amplifier architecture that was readily amenable to known, predictable modifications, such as implementing it in an embedded system (per Luk) and using a standard, advanced isolation technique like STI (per Takemura).
  • Additional Grounds: Petitioner asserted an additional obviousness challenge for claims 4-6 over Aoyama, Luk, and Hidaka, relying on a similar rationale of substituting known isolation techniques (Hidaka's field shield electrode) into a base sense-amplifier design (Aoyama).

4. Key Claim Construction Positions

  • "Parallel" (claims 1, 4): Petitioner proposed this term should be construed to mean "side by side and having the same distance continuously between them." This construction was asserted to be consistent with the patent's figures and was important for demonstrating that the linear, equidistant layouts shown in prior art like Hidaka and Aoyama met this claim limitation.
  • "[F]ield shield electrode" (claim 4): Petitioner proposed this term means an "electrode separate from the N-type and P-type sense amplifier transistors that employs a field effect to electrically isolate two adjacent transistors." This construction aimed to define the element as a distinct isolation structure, separate from the active transistors, which Petitioner argued was consistent with its known meaning in the art and as taught by references like Hidaka.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate. It asserted that it filed the petition with "extraordinary diligence," less than three months after being sued and before any significant district court activity had occurred, such as a case management conference or scheduling order. Petitioner also contended that the merits of the petition are strong, especially since none of the cited prior art was considered during prosecution, and that institution would promote systemic efficiency. Finally, Petitioner noted a potential lack of complete overlap, as the IPR challenges claims (4-6) not explicitly identified in the district court complaint.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1 and 4-6 of Patent 6,747,320 as unpatentable.