PTAB

IPR2020-01009

Micron Technology Inc v. Godo Kaisha IP Bridge

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: SEMICONDUCTOR DEVICE WITH DRAM INSIDE
  • Brief Description: The ’320 patent relates to a Dynamic Random Access Memory (DRAM) semiconductor device featuring a specific sense amplifier design. The design arranges pairs of N-type and P-type transistor gate electrodes in a linear fashion, parallel to each other and to the DRAM bit lines, to suppress differences in electrical characteristics between adjacent sense amplifiers.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claim 1 over Hidaka, Luk, and Takemura

  • Prior Art Relied Upon: Hidaka (Patent 6,018,172), Luk (Patent 5,883,814), and Takemura (Patent 6,477,100).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the primary reference, Hidaka, disclosed the core structure of the challenged claim: a DRAM with CMOS sense amplifiers having pairs of N-type and P-type transistor gates arranged parallel to each other and to the bit lines over a common active region. To meet the "co-resident" logic region limitation, Petitioner asserted Luk taught the known practice and benefits of embedding such a DRAM on a single chip with a separate logic processor. To meet the shallow trench isolation (STI) limitation, Petitioner pointed to Takemura, which taught using STI to isolate adjacent, similar sense amplifiers.
    • Motivation to Combine: A POSITA would combine Luk with Hidaka to achieve the well-known benefits of embedded DRAM, such as increased integration, higher speed, and lower power consumption. A POSITA would be further motivated to replace Hidaka’s older LOCOS isolation with the STI taught by Takemura to create a more compact, efficient memory device, which was a clear design goal in the art.
    • Expectation of Success: Petitioner contended that combining these known elements was a routine design choice. Implementing Hidaka’s DRAM in an embedded configuration using Luk’s teachings, and substituting a known, superior isolation method (STI from Takemura) for an older one (LOCOS from Hidaka), would have been straightforward with a high expectation of success.

Ground 2: Obviousness of Claims 4-6 over Hidaka and Luk

  • Prior Art Relied Upon: Hidaka (Patent 6,018,172) and Luk (Patent 5,883,814).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground challenged claims requiring a "field shield electrode" for isolation instead of STI. Petitioner asserted that Hidaka taught all limitations of independent claim 4, including the use of a field shield electrode as a disclosed alternative to LOCOS isolation for separating adjacent transistors. The arrangement of this electrode between and parallel to the sense amplifier gates was allegedly shown in Hidaka’s figures. The combination with Luk satisfied the embedded DRAM limitation for the same reasons as in Ground 1. For dependent claim 5, Petitioner argued Hidaka’s symmetrical layouts taught disposing electrodes at a "substantially equal interval." For claim 6, a related patent, Hidaka II, was cited to show that applying a ground or negative potential to such a field shield electrode was a known technique.
    • Motivation to Combine: The motivation to combine Hidaka and Luk was identical to Ground 1. The motivation to use Hidaka’s own disclosed field shield electrode was simply that it was a known, available, and more compact alternative to LOCOS, making it a predictable design choice for a POSITA implementing Hidaka's teachings.
    • Expectation of Success: Petitioner argued a POSITA would have reasonably expected to successfully combine Luk’s embedding techniques with Hidaka’s DRAM. Further, there was a high expectation of success in using the field shield isolation method explicitly disclosed within Hidaka as an alternative isolation structure.

Ground 3: Obviousness of Claim 1 over Aoyama, Luk, and Takemura

  • Prior Art Relied Upon: Aoyama (Patent 4,730,280), Luk (Patent 5,883,814), and Takemura (Patent 6,477,100).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presented an alternative to Ground 1, with Aoyama serving as the primary reference. Petitioner argued Aoyama taught a DRAM with CMOS sense amplifiers where the gate electrodes are arranged parallel to each other and to the bit lines, satisfying the core structural limitations of claim 1. As in Ground 1, Luk was cited to supply the teaching of embedding the DRAM with co-resident logic, and Takemura was cited to provide the specific teaching of using STI to isolate the adjacent sense amplifiers shown in Aoyama.
    • Motivation to Combine: The motivations were analogous to Ground 1. A POSITA would combine Aoyama’s DRAM with Luk’s embedding architecture to achieve performance benefits. A POSITA would also be motivated to use the modern, space-efficient STI method from Takemura to implement the necessary isolation between Aoyama’s sense amplifiers, which was a known problem with a known solution.
    • Expectation of Success: Petitioner asserted a reasonable expectation of success, as the combination involved applying a known integration strategy (embedding from Luk) and a standard, improved isolation technique (STI from Takemura) to a conventional DRAM sense amplifier design (Aoyama).

  • Additional Grounds: Petitioner asserted an additional obviousness challenge for claims 4-6 over Aoyama, Luk, and Hidaka, which relied on similar arguments but used Hidaka to supply the "field shield electrode" teaching to Aoyama's base design.

4. Key Claim Construction Positions

  • "Parallel" (claims 1, 4): Petitioner proposed this term be construed as "side by side and having the same distance continuously between them." This construction was argued to be consistent with the plain meaning and the patent’s figures, ensuring that prior art references with linear, equidistant gate and bit line layouts met the claim limitation.
  • "[F]ield shield electrode" (claim 4): Petitioner proposed this term meant "an electrode separate from the N-type and P-type sense amplifier transistors that employs a field effect to electrically isolate two adjacent transistors." This construction was critical to mapping the isolation structures disclosed in Hidaka to the specific language of claim 4.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was inappropriate. It asserted that the petition was filed diligently, less than three months after the co-pending district court litigation was initiated and before any significant investment in the parallel proceeding had occurred (e.g., no case schedule was set). Petitioner also contended that the strong merits of the petition weighed in favor of institution to promote system efficiency and integrity.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1 and 4-6 of the ’320 patent as unpatentable.