NXP Semiconductors NV v. Bell Seminconductor LLC

1. Case Identification

• Case #: IPR2021-00966
• Patent #: 8,049,340
• Filed: May 17, 2021
• Petitioner(s): NXP BV., NXP USA, Inc., NXP Semiconductors N.V.
• Patent Owner(s): Bell Semiconductor, LLC
• Challenged Claims: 1-19

2. Patent Overview

• Title: Integrated Circuit Package Substrate
• Brief Description: The ’340 patent describes an integrated circuit (IC) package substrate designed to reduce parasitic capacitance between electrical connection pads and internal metal layers. The invention involves creating cutouts in metal layers adjacent to the pads to increase the distance to the nearest metal, thereby improving signal integrity in high-frequency circuits.

3. Grounds for Unpatentability

Ground 1: Obviousness over Chin - Claims 1, 3, 4, 6-9, and 12-15 are obvious over Chin.

• Prior Art Relied Upon: Chin (Patent 6,765,298).
• Core Argument for this Ground: Petitioner argued that Chin taught a nearly identical solution to the same problem addressed by the ’340 patent—reducing parasitic capacitance of pads on a package substrate.
  • Prior Art Mapping: Chin disclosed a multi-layered printed circuit board (PCB) or package substrate with "patterned holes" (the claimed "cutouts") in underlying metallic layers, aligned with contact pads to reduce capacitance. Petitioner asserted that Chin's teachings on PCBs were explicitly made applicable to package substrates, including ball-grid-array (BGA) types. Chin was argued to disclose a first conductive layer with contact pads and a second conductive layer with cutouts that overlap the pads, separated by a dielectric layer, meeting the core limitations of independent claim 1.
  • Motivation to Combine (for §103 grounds): As a single-reference ground, the argument was that a person of ordinary skill in the art (POSITA) would have found it obvious to apply Chin's teachings directly. For dependent claims, such as sizing the cutouts to match the pads (claim 3), Petitioner argued this was a simple design choice with predictable trade-offs between capacitance reduction and signal shielding, making it obvious to try.
  • Expectation of Success: A POSITA would have had a high expectation of success because Chin was directed to the very same technical problem and provided a clear, detailed solution for achieving the desired reduction in parasitic capacitance.

Ground 2: Obviousness over Chin, MC92600, and HighSpeed - Claims 2, 4, 5, and 10 are obvious over Chin in view of MC92600 and HighSpeed.

• Prior Art Relied Upon: Chin (Patent 6,765,298), MC92600 (a Motorola SERDES Reference Manual), and HighSpeed (a design handbook).
• Core Argument for this Ground: This ground asserted that it would have been obvious to implement the SERDES (Serializer/Deserializer) functionality and specific routing layer configurations recited in the dependent claims within Chin's basic substrate structure.
  • Prior Art Mapping: Chin provided the substrate with capacitance-reducing cutouts. MC92600, a reference manual for a commercial SERDES product, was cited to show that arranging BGA ball pads into distinct "transmit" and "receive" rows was a known, industry-standard practice for high-speed communication. HighSpeed was cited as a general design reference teaching common techniques, such as using a routing layer with traces immediately adjacent to the contact pad layer and connecting them with vias.
  • Motivation to Combine (for §103 grounds): A POSITA designing a high-speed package substrate like Chin's would be motivated to consult references for standard high-speed interface configurations. A POSITA would combine Chin's capacitance reduction technique with the industry-standard SERDES pinout from MC92600 for compatibility and performance. The POSITA would further look to a standard design guide like HighSpeed for well-known methods of arranging and connecting routing layers to implement that interface.
  • Expectation of Success: The combination involved applying known, standard design elements (SERDES pinouts, routing layers) to a known substrate design (Chin) to achieve the predictable result of a functional high-speed package.

Ground 3: Obviousness over Chin and Oggioni - Claims 3 and 11 are obvious over Chin in view of Oggioni.

• Prior Art Relied Upon: Chin (Patent 6,765,298) and Oggioni (Patent 6,717,255).

• Core Argument for this Ground: This ground addressed the specific limitation that the cutouts have the "same dimensions as the contact pads," which Petitioner argued was an obvious design choice taught by Oggioni to solve a known problem with Chin's approach.

  • Prior Art Mapping: Chin taught using cutouts that were larger than the contact pads but acknowledged this design could create an "impedance discontinuity." Oggioni was presented as teaching a solution to the same capacitance problem by using cutouts ("non-intersecting regions") that were the same size as the contact pads, which avoided the impedance issue.
  • Motivation to Combine (for §103 grounds): A POSITA starting with Chin's design would recognize the impedance problem caused by oversized cutouts. In seeking a solution, the POSITA would have been motivated to look at other art in the same field, like Oggioni, which provided the solution of making the cutout the same size as the pad. This was argued to be a simple substitution of one known element for another to optimize performance and obtain predictable results.
  • Expectation of Success: A POSITA would have a high expectation of success in modifying Chin's design with Oggioni's teaching, as it was a straightforward design modification to address a known trade-off.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including Shafer (for arranging contacts in transmit/receive rows to reduce crosstalk), Hsu and Barr (for specific via fabrication techniques within cutouts), and various permutations of these references.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) based on Fintiv factors was unwarranted. The petition was filed as a "copycat" of an already-instituted inter partes review (IPR), IPR2021-00148, and was accompanied by a motion for joinder, which Petitioner contended obviates concerns of serial challenges. Petitioner stipulated that, if the IPR were instituted, it would not pursue any ground raised or that could have been reasonably raised in the parallel district court litigation, a factor weighing strongly against denial. Further, Petitioner argued that substantial work remained in the district court case and that institution would efficiently resolve invalidity issues across multiple litigations involving the ’340 patent.

5. Relief Requested

• Petitioner requested the institution of an IPR and cancellation of claims 1-19 of Patent 8,049,340 as unpatentable under 35 U.S.C. §103.