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IPR2021-01064

OpenSky Industries LLC v. VLSI Technology LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Managing Clock Frequency in an Electronic Device
  • Brief Description: The ’759 patent describes methods and systems for dynamically managing clock frequency in a multi-device computing environment. The core concept involves a first "master device" requesting a change in clock speed in response to a predefined change in its performance (e.g., due to loading), which then causes a clock controller to provide a high-speed clock signal to a second master device and a shared bus.

3. Grounds for Unpatentability

Ground 1: Claims 1, 14, and 17 are obvious over Shaffer in view of Lint.

  • Prior Art Relied Upon: Shaffer (Patent 6,298,448) and Lint (Patent 7,360,103).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Shaffer taught the core elements of the claims, including a system with multiple master devices (a CPU and controllers) coupled to a bus. In Shaffer, a CPU monitors its own utilization and sends a request (an instruction) to a programmable clock module to increase or decrease its clock frequency. Shaffer further disclosed that the adjusted clock signal from this module drives the entire system bus and other controllers, thereby controlling the clock frequency of a second master device. Petitioner asserted that Lint was added to supply the limitation of measuring performance "within a predefined time interval." While Shaffer taught changing frequency based on CPU utilization, Lint explicitly described a well-known technique of measuring processor utilization as the percentage of cycles spent on useful work during a "last predetermined interval" to determine the appropriate clock speed for the next interval.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Lint's detailed, interval-based performance measurement with Shaffer's system to improve its power management capabilities. Petitioner argued this was a predictable combination, as both references addressed the same problem of saving power by adjusting clock speed based on processor load, and Lint's method represented a well-known, more specific implementation of the general concept taught in Shaffer.
    • Expectation of Success: A POSITA would have a high expectation of success, as the combination involved applying a known, detailed measurement technique (Lint) to a known type of system (Shaffer) to achieve the predictable result of more refined power management.

Ground 2: Claims 18, 21-22, and 24 are obvious over Shaffer in view of Lint and Kiriake.

  • Prior Art Relied Upon: Shaffer (Patent 6,298,448), Lint (Patent 7,360,103), and Kiriake (Application # 2003/0159080).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground incorporated the teachings of Shaffer and Lint from Ground 1 and added Kiriake to teach the arbiter limitation present in claims 18, 21-22, and 24. Petitioner asserted that Kiriake disclosed an arbiter coupled to a system bus and multiple master devices (peripheral processors). The arbiter in Kiriake performed arbitration by receiving bus requests and issuing grants to control the flow of data on the bus. This structure and function directly mapped to the claimed arbiter.
    • Motivation to Combine: A POSITA would be motivated to add an arbiter, as taught by Kiriake, to the multi-device system of Shaffer. Because Shaffer's system involved multiple master devices (CPUs, controllers) sharing a limited resource (the system bus), managing access to prevent conflicts was a known problem with a standard solution: arbitration. Adding an arbiter was a conventional step to ensure predictable system operation.
    • Expectation of Success: Integrating a standard arbiter into a multi-master bus system was a routine design choice at the time, leading to a high expectation of success in achieving predictable bus control.

Ground 3: Claims 1, 14, and 17 are obvious over Chen in view of Terrell.

  • Prior Art Relied Upon: Chen (Patent 5,838,995) and Terrell (Application # 2004/0098631).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Chen disclosed a system with multiple master devices on a bus where a device could request a higher clock speed from a clock gate logic based on its capability to handle a "particular transaction." Terrell was introduced to teach triggering clock speed changes based on the actual, measured performance needs of a device rather than just its maximum capability. Terrell specifically taught measuring processor workload (e.g., "idleness") over a "sample period" and adjusting the clock frequency to the minimum level required, thereby saving power.
    • Motivation to Combine: A POSITA would combine Terrell's need-based performance monitoring with Chen's capability-based system to achieve superior power efficiency. Terrell expressly stated its features were "desirable" for systems like Chen's. Modifying Chen's system to request higher speeds only when needed (per Terrell), rather than just when possible, was a known method for improving power consumption.
    • Expectation of Success: The combination involved using a known technique (workload measurement) to improve a similar device (Chen's system) in a predictable way (reducing power consumption), leading to a reasonable expectation of success.

Ground 4: Claims 18, 21-22, and 24 are obvious over Chen in view of Terrell and Kiriake.

  • Prior Art Relied Upon: Chen (Patent 5,838,995), Terrell (Application # 2004/0098631), and Kiriake (Application # 2003/0159080).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Chen and Terrell from Ground 3, adding Kiriake to supply the arbiter limitation. Petitioner argued that Kiriake’s arbiter, which controlled bus access for multiple master devices, would be integrated with Chen's bridge control logic.
    • Motivation to Combine: A POSITA would be motivated to incorporate Kiriake's explicit arbiter into Chen's multi-master system to formalize the control of bus access. Chen already described arbitration cycles for initiating transactions, making the inclusion of a dedicated arbiter component a well-known and logical design improvement for managing bus traffic efficiently and predictably.
    • Expectation of Success: As with Ground 2, adding a standard arbiter to a multi-master system was a conventional and predictable design modification.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate. The petition was filed after a district court trial between the Patent Owner and a third party (Intel) had concluded. Petitioner asserted that nearly every Fintiv factor weighed in favor of institution because: (1) Petitioner is unrelated to Intel; (2) the trial had already finished, eliminating concerns about parallel proceedings; (3) the specific prior art and invalidity grounds presented in the petition were never raised, considered, or decided by the district court judge or jury; and (4) the petition challenged additional claims not at issue in the litigation. Petitioner emphasized that instituting review was necessary to protect the integrity of the patent system, as a jury had awarded a substantial verdict without any court or tribunal ever assessing the validity of the challenged claims.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 14, 17-18, 21-22, and 24 of the ’759 patent as unpatentable under 35 U.S.C. §103.