Micron Technology Inc v. Besang Inc

1. Case Identification

• Case #: IPR2023-00900
• Patent #: 7,378,702
• Filed: May 4, 2023
• Petitioner(s): Micron Technology, Inc, Micron Semiconductor Products, Inc., and Micron Technology Texas, LLC
• Patent Owner(s): BeSang Inc.
• Challenged Claims: 13-17

2. Patent Overview

• Title: Vertically Oriented Semiconductor Memory Structure and Method of Manufacturing
• Brief Description: The ’702 patent discloses a three-dimensional integrated circuit structure. The technology involves forming vertically oriented semiconductor memory cells on a separate "stackable add-on layer" which is then bonded to a primary substrate that already contains electrical devices and interconnects to achieve higher integration density.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claim 13 over Watanabe

• Prior Art Relied Upon: Watanabe (Patent 5,091,762).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Watanabe alone discloses all elements of independent claim 13. Watanabe teaches a substrate with peripheral circuits (electrical devices) and an overlying insulating film (dielectric layer). It describes a "stacking method" where "planar members" (the claimed "stackable add-on layer") containing vertically oriented memory cells are fabricated on separate substrates and then bonded to the primary substrate. Watanabe further teaches that its methods are applicable to nonvolatile memory like EPROM, satisfying the final limitation of the claim.
  • Motivation to Combine (for §103 grounds): As a single-reference ground, the motivation was inherent in Watanabe’s own disclosure, which aimed to provide a high-density, three-dimensional semiconductor memory device.
  • Expectation of Success (for §103 grounds): Success was expected as Watanabe’s own methods were described as achieving the claimed configuration.

Ground 2: Obviousness of Claims 14-17 over Watanabe in view of Endoh

• Prior Art Relied Upon: Watanabe (Patent 5,091,762), Endoh (Application # US2002/0154556).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground asserted that Watanabe provides the basic structure of claim 13, and Endoh supplies the specific features required by dependent claims 14-17. For claim 14 (SOI pillar), Endoh explicitly taught forming vertical memory cells on Silicon-On-Insulator (SOI) pillars. For claim 15 (charge-trapping gate), Endoh taught using charge-trapping insulators as a well-known alternative to the floating gates in Watanabe's EPROM. For claims 16 and 17 (serially connected cells on one or more pillars), Endoh taught a NAND architecture where cells are connected in series to increase density, a known technique applicable to Watanabe’s pillar structures.
  • Motivation to Combine (for §103 grounds): A POSITA, seeking to improve the density and performance of Watanabe's 3D memory, would combine it with Endoh’s well-known and advantageous techniques. Using an SOI pillar improves device isolation, substituting a charge-trapping gate improves reliability and scalability, and implementing a NAND serial connection dramatically increases storage density.
  • Expectation of Success (for §103 grounds): Success was expected because both references address increasing memory density, and the combination involved applying predictable and well-understood semiconductor technologies to achieve their known benefits.

Ground 3: Obviousness of Claims 13-15 over Lee

• Prior Art Relied Upon: Lee (Patent 6,881,994).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Lee alone renders the claims obvious, particularly under a construction where "stackable add-on layer" includes monolithic, sequential deposition. Lee discloses a substrate with driver circuits (electrical devices) beneath a dielectric layer. Upon this, Lee teaches forming a monolithic 3D array of vertically oriented, nonvolatile memory cells in pillars. Lee also explicitly discloses forming these pillars on an SOI substrate (claim 14) and teaches that the memory cells can use either a floating gate or a charge-trapping dielectric (claim 15).
  • Motivation to Combine (for §103 grounds): As a single-reference ground, the motivation was inherent in Lee’s own objective to create an "ultra-dense" nonvolatile memory array.
  • Expectation of Success (for §103 grounds): Lee’s detailed disclosure of fabrication methods for its described structures ensured a reasonable expectation of success.

Ground 4: Obviousness of Claims 13-15 over Lee in view of Watanabe

• Prior Art Relied Upon: Lee (Patent 6,881,994), Watanabe (Patent 5,091,762).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground was presented as an alternative, addressing a claim construction where "stackable add-on layer" requires separate fabrication and subsequent bonding, a method not taught by Lee's monolithic approach. Lee provided the teachings for the vertical nonvolatile memory cells and the underlying substrate with devices. Watanabe provided the missing process step: its "stacking method" explicitly teaches fabricating such memory layers separately and then bonding them to the final substrate.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Lee's cell design with Watanabe's well-known alternative "stacking" fabrication method. This would be done to obtain the benefits Watanabe associated with its bonding method, such as improved wiring accuracy, while using the advanced cell structures disclosed in the more recent Lee reference.
  • Expectation of Success (for §103 grounds): A POSITA would have reasonably expected success in applying a known fabrication and bonding technique (from Watanabe) to a known cell design (from Lee), as both were established methods for building 3D memory.

• Additional Grounds: Petitioner asserted additional obviousness challenges for claims 16-17 based on combinations of Lee, Endoh, and Watanabe, relying on similar motivations to implement high-density NAND serial connections and alternative fabrication methods.

4. Key Claim Construction Positions

• Petitioner’s arguments centered on the term "stackable add-on layer," contending that the claims are unpatentable regardless of how it is construed.
• Petitioner addressed two interpretations: (1) a broad construction covering monolithic, layer-by-layer deposition, which Petitioner argued was taught by Lee alone; and (2) a narrower construction requiring separate fabrication of the layer followed by bonding, which Petitioner argued was taught by Watanabe and would be obvious to combine with Lee.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) pursuant to the Fintiv factors would be inappropriate.
• The core arguments were that the co-pending district court case was at a very early stage with minimal investment from the parties or the court, and the estimated trial date was not significantly earlier than the expected date for a Final Written Decision (FWD). Petitioner asserted that the strong merits of the petition and the IPR's potential to simplify issues for trial weighed heavily against denial.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 13-17 of Patent 7,378,702 as unpatentable under 35 U.S.C. §103.