PTAB

IPR2023-00900

Micron Technology Inc v. BeSang Inc

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: 3-D Integrated Circuit and Method of Forming Same
  • Brief Description: The ’702 patent discloses a three-dimensional integrated circuit structure. The core technology involves creating vertically oriented semiconductor memory cells in a separately fabricated "stackable add-on layer," which is then bonded to a base substrate that contains its own electrical devices and interconnections.

3. Grounds for Unpatentability

Ground 1: Claims 14-17 are obvious over Watanabe in view of Endoh

  • Prior Art Relied Upon: Watanabe (Patent 5,091,762) and Endoh (Application # US2002/0154556).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Watanabe taught the foundational elements of a three-dimensional memory device, including vertically stacked, nonvolatile memory cells on a substrate with a dielectric layer. However, Watanabe’s teachings were general. Endoh allegedly supplied specific, well-known implementations for the additional limitations in the dependent claims. Specifically, Petitioner argued a POSITA would combine Watanabe's structure with Endoh's teachings to implement a vertical transistor on a Silicon-On-Insulator (SOI) pillar (claim 14), use a charge-trapping gate insulator as a known alternative to a floating gate (claim 15), serially connect memory cells to form a high-density NAND string (claim 16), and use an interconnect line to connect multiple pillars in series (claim 17).
    • Motivation to Combine: A POSITA would combine these references to increase the integration density of the memory device, which was a primary goal of both patents. Endoh’s teachings on SOI pillars and NAND architecture were known methods to reduce chip area, decrease production costs, and improve performance, directly aligning with the objectives of Watanabe.
    • Expectation of Success: Petitioner argued there would be a high expectation of success because both references address the same technical field and problems with complementary, predictable solutions. The use of SOI substrates and NAND architecture were well-established techniques in semiconductor memory design.

Ground 2: Claims 13-15 are obvious over Lee

  • Prior Art Relied Upon: Lee (Patent 6,881,994).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Lee alone disclosed all limitations of independent claim 13 and dependent claims 14-15. Lee was said to teach a "monolithic three dimensional array" of memory devices, which included a substrate with driver circuits beneath an insulating layer, meeting limitation 13[a]. The array itself, comprised of vertically oriented "pillar" memory cells (TFT EEPROMs), constituted the "stackable add-on layer" of limitation 13[b]. Petitioner argued that Lee’s "monolithic" method, involving direct sequential deposition of layers, inherently "bonded" the stackable layer to the dielectric layer (13[c]). The cells were described as nonvolatile EEPROMs, satisfying limitation 13[d]. Furthermore, Lee allegedly disclosed using an SOI substrate and structures with floating gates (addressing claim 14) and charge-trapping layers as an alternative (addressing claim 15).

Ground 3: Claims 13-15 are obvious over Lee in view of Watanabe

  • Prior Art Relied Upon: Lee (’994 patent) and Watanabe (’762 patent).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground was presented as an alternative argument, contingent on the term "bonded" being construed to require separate fabrication and subsequent attachment, a process not taught by Lee's "monolithic" approach. While Lee taught forming a 3D structure via layer-by-layer sequential deposition, Watanabe taught both this "laminating method" and a "stacking method" where "planar members" (stackable layers) were fabricated on separate substrates and then bonded together.
    • Motivation to Combine: A POSITA, starting with Lee's 3D memory structure, would have been motivated to substitute Lee's monolithic fabrication process with Watanabe’s "stacking method." Watanabe explicitly taught that its stacking method offered benefits such as improved wiring accuracy and lower interconnection resistance, providing a clear reason for its adoption.
    • Expectation of Success: Success was expected because Watanabe’s stacking method was presented as a known, viable alternative for creating 3D memory structures, achieving the same objectives as Lee’s monolithic method.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claim 13 is obvious over Watanabe alone; claims 16 and 17 are obvious over Lee in view of Endoh; and claims 16 and 17 are obvious over the combination of Lee, Watanabe, and Endoh.

4. Key Claim Construction Positions

  • Petitioner argued that the grounds for unpatentability are robust under multiple potential constructions of key claim terms. The central issue highlighted was the interpretation of "a stackable add-on layer ... being bonded to the dielectric layer" in claim 13. Petitioner contended its arguments prevail whether this phrase permits monolithic, sequential deposition (as taught by Lee) or requires the layer to be fabricated separately and subsequently attached (as taught by Watanabe's "stacking method"). Ground 5 was presented specifically to address the latter construction.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that the Board should not issue a discretionary denial under Fintiv. The core arguments were:
    • The co-pending district court litigation (BeSang Inc. v. Micron Tech., Inc.) is in a very early stage, with no trial date, claim construction hearing, or significant discovery having occurred.
    • The scope of the inter partes review (IPR) is broader than the district court case. While the litigation complaint asserted only claim 13, the IPR challenges claims 13-17, meaning the IPR is the only venue where the patentability of claims 14-17 will be adjudicated, thus promoting efficiency.
    • The petition presents strong merits for unpatentability based on multiple combinations of prior art that were not considered during prosecution.

6. Relief Requested

  • Petitioner requests institution of IPR and cancellation of claims 13-17 of the ’702 patent as unpatentable.