PTAB

IPR2023-00991

Intel Corp v. BeSang Inc

Log In

1. Case Identification

2. Patent Overview

  • Title: Vertically Oriented Memory Devices and Methods of Fabrication
  • Brief Description: The ’702 patent describes vertically oriented semiconductor memory cells (e.g., DRAM, SRAM) formed in a "stackable add-on layer" that is added to a separately fabricated substrate containing electrical devices and interconnects. The vertical orientation is intended to increase memory density on a chip.

3. Grounds for Unpatentability

Ground 1A: Obviousness over Lee (Claims 13-17)

  • Prior Art Relied Upon: Lee (Application # 2002/0028541).
  • Core Argument for this Ground: This ground argued that the claims were obvious under the Patent Owner's apparent broad construction of "bonded," where it encompasses any direct or indirect adherence.
    • Prior Art Mapping: Petitioner asserted that Lee’s Figure 35 discloses the foundational structure: a substrate with driver circuits (“electrical devices”), an insulating layer (“dielectric layer”) above them, and a stackable memory array level on top. Lee further disclosed various vertically oriented, nonvolatile pillar memory cells (in its Figures 1A, 2, 7, and 25A) that could be used in the memory array. This combination of teachings allegedly disclosed all limitations of independent claim 13 and its dependent claims, which recite specific vertical transistor features taught in Lee's various pillar embodiments.
    • Motivation to Combine (for §103 grounds): A POSITA would combine the teachings of Lee’s various figures because Lee explicitly stated that the pillar devices were preferred embodiments for its memory array. Using these vertical cells would further Lee’s stated goal of increasing memory device density by reducing lateral surface area.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success as Lee expressly contemplated using these memory cells in its array structure, making the results of the combination predictable.

Ground 1C: Obviousness over Lee and Kim (Claims 13-17)

  • Prior Art Relied Upon: Lee (Application # 2002/0028541), Kim (Application # 2003/0157748).
  • Core Argument for this Ground: This ground argued for obviousness under Petitioner's proposed construction of "bonded" as requiring wafer bonding.
    • Prior Art Mapping: Petitioner argued that while Lee disclosed the base structure with vertically oriented memory cells, it did not clearly describe how the first memory layer was attached. Kim supplied this missing element by teaching a three-dimensional, wafer-to-wafer vertical stacking process using a dielectric layer. In the proposed combination, Lee's memory cell array would be fabricated on a separate wafer and then wafer-bonded to Lee’s substrate wafer (containing driver circuits) using the method taught by Kim.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Lee with Kim to implement Lee’s stackable memory array as a non-monolithic device, which Kim taught was advantageous for logic/memory stacking. This approach would also allow for more efficient quality control, as the memory wafer could be tested before bonding, minimizing waste—a known benefit of wafer-bonding techniques.
    • Expectation of Success (for §103 grounds): Success would be expected because Kim demonstrated that wafer-bonding memory and logic wafers was a known technique for its intended purpose of creating 3D integrated circuits.

Ground 3: Obviousness over Park and Kim (Claim 1)

  • Prior Art Relied Upon: Park (Patent 5,571,730), Kim (Application # 2003/0157748).
  • Core Argument for this Ground: This ground specifically targeted claim 1, which requires DRAM memory cells.
    • Prior Art Mapping: Petitioner contended that Kim disclosed a substrate with active IC devices (e.g., microprocessors), an interlayer dielectric, and an interconnect layer, consistent with claim limitation 1[a]. Kim also taught bonding a second wafer containing memory devices on top of this first wafer. Park disclosed the features of this second wafer: a "first stackable add-on layer" including a plurality of vertically oriented DRAM memory cells, where the cells are separated by dielectric material, meeting limitation 1[b]. The combined structure would have the stackable add-on layer bonded to a layer of the substrate at the greatest distance from its bottom surface, satisfying 1[c].
    • Motivation to Combine (for §103 grounds): A POSITA would combine Park’s vertically structured DRAM with Kim’s 3D wafer stacking to further the express goal of both references: increasing integration and system performance. This combination represented applying a known technique (Kim's stacking) to a known device ready for improvement (Park's vertical DRAM) to achieve predictable results.
    • Expectation of Success (for §103 grounds): Kim showed that wafer-bonding a memory wafer to a logic wafer was within the skill of a POSITA, and both Park's and Kim's teachings would be employed for their intended purposes, providing a reasonable expectation of success.
  • Additional Grounds: Petitioner asserted multiple additional obviousness challenges, including claims 16-17 over Lee and Endoh (Application # 2002/0154556); claims 13-17 over Lee and Aspar (a 2001 journal article); claim 13 over Johnson (Patent 6,034,882) alone and in view of Kim or Aspar. These grounds relied on similar theories of either monolithic deposition or wafer bonding to achieve the claimed structures.

4. Key Claim Construction Positions

  • "Stackable add-on layer ... [is]/[being] bonded" (Claims 1, 13): Petitioner argued this phrase requires that the add-on layer is a distinct, separately formed structure that is attached via wafer bonding to the underlying substrate. This contrasts with the Patent Owner's potential broader interpretation that could include monolithic deposition.
  • "SOI pillar" (Claims 14–17): Petitioner contended this term requires a pillar-shaped, doped, stacked structure formed within a stackable add-on layer that was itself added using Silicon-on-Insulator (SOI) technology, such as the Smart-Cut® process. This construction is narrower than any pillar-shaped structure with an insulator below it.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be inappropriate.
  • Fintiv: No trial date had been set in the parallel district court litigation, and the average time to trial in that venue (District of Oregon) was 46.3 months, ensuring the PTAB’s Final Written Decision would issue first.
  • General Plastic: Petitioner argued against denial based on a co-pending IPR filed by another party (Micron), stating that Intel and Micron are not co-defendants, do not have a substantial relationship, and do not challenge the exact same set of claims. Further, this petition was filed before the Patent Owner Preliminary Response in the Micron IPR, alleviating concerns of "road-mapping."

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1 and 13-17 of the ’702 patent as unpatentable.