PTAB

IPR2023-00991

InTel Corp v. BeSang Inc

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1. Case Identification

2. Patent Overview

  • Title: Vertically Oriented Semiconductor Memory Structures
  • Brief Description: The ’702 patent relates to semiconductor memory structures featuring vertically oriented memory cells (e.g., DRAM, SRAM, or nonvolatile memory) formed within a "stackable add-on layer." This layer is added to a separately fabricated substrate containing electrical devices and interconnects, aiming to increase memory density for a given chip area.

3. Grounds for Unpatentability

Ground 1A: Obviousness of Claims 13-17 over Lee

  • Prior Art Relied Upon: Lee (Application # 2002/0028541).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lee disclosed all limitations of claims 13-17. Lee's Figure 35 showed a memory structure with a substrate containing driver circuits (electrical devices) and an overlying dielectric layer. On this dielectric, Lee taught forming a memory array (a "stackable add-on layer") comprising vertically oriented, nonvolatile memory cells. Petitioner contended that various embodiments within Lee (e.g., Figs. 1A, 2, 7, 25A) explicitly taught the specific vertical, nonvolatile memory cell structures required by dependent claims 14-17, such as those with floating gates or charge-trapping insulators on pillar structures.
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would be motivated to implement the vertical cell structures of Lee’s Figures 1A, 2, 7, or 25A within the array of Lee’s Figure 35, as Lee itself expressly described these as preferred embodiments for creating high-density, stackable memory.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because Lee explicitly contemplated using these pillar-type memory devices in its array, making it a predictable implementation.

Ground 1C: Obviousness of Claims 13-17 over Lee and Kim

  • Prior Art Relied Upon: Lee (Application # 2002/0028541), Kim (Application # 2003/0157748).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground asserted that, under a proper construction where "bonded" requires wafer bonding, Kim supplied the missing teaching. Lee provided the basic elements of a substrate with driver circuits and a separate layer of vertical memory cells. Kim taught a method for creating a 3-D vertical stack by wafer-bonding a memory device wafer to a logic device wafer across a dielectric layer. The combination resulted in Lee's memory cell layer ("stackable add-on layer") being wafer-bonded to Lee's substrate with driver circuits, as taught by Kim.
    • Motivation to Combine (for §103 grounds): Petitioner argued that Lee’s disclosure was unclear on how its memory layer was formed, which would motivate a POSITA to look to known fabrication techniques. A POSITA would combine Kim's wafer bonding with Lee's structure to create a non-monolithic device, thereby improving quality control and reducing waste compared to monolithic deposition, a known benefit of wafer-level stacking.
    • Expectation of Success (for §103 grounds): Success was predictable, as Kim explicitly taught logic/memory stacking, making the integration of Lee's respective components a straightforward application of a known technique to achieve a known result.

Ground 3: Obviousness of Claim 1 over Park and Kim

  • Prior Art Relied Upon: Park (Patent 5,571,730), Kim (Application # 2003/0157748).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground targeted claim 1's DRAM limitation. Park taught vertically structured DRAM cells formed in silicon pillars to achieve high integration. Kim taught 3D wafer-to-wafer stacking, where a memory wafer is bonded to a logic wafer. In the proposed combination, Kim's second wafer (the "stackable add-on layer") would be fabricated with Park’s vertically oriented DRAM cells, and this memory wafer would be bonded to Kim's first wafer containing logic devices (the "substrate").
    • Motivation to Combine (for §103 grounds): A POSITA would be motivated to stack Park's vertical DRAM cells onto a logic wafer using Kim's bonding technology to further the explicit goal of both references—increasing integration. This combination would also yield Kim's stated benefits of shortening wire lengths, reducing RC delay, and increasing overall system performance.
    • Expectation of Success (for §103 grounds): The combination involved the simple substitution of one known memory type (Park's DRAM) into a known wafer-stacking process (Kim's), which would have yielded the predictable result of a 3D logic-memory integrated circuit.

  • Additional Grounds: Petitioner asserted numerous other obviousness challenges, including combinations of Lee with Endoh; Lee with Aspar; Johnson alone; Johnson with Kim; and Johnson with Aspar, which relied on similar principles of substituting known vertical memory cell designs and wafer bonding techniques.

4. Key Claim Construction Positions

  • "Stackable add-on layer … bonded" (Claims 1, 13): Petitioner contended this term requires the "stackable add-on layer" to be a pre-fabricated structure that is subsequently attached to the substrate via wafer bonding. This construction is contrary to monolithic deposition, where layers are grown sequentially on the substrate.
  • "SOI pillar" (Claims 14–17): Petitioner asserted this term requires a pillar-shaped, doped-stack structure that is formed within a stackable add-on layer that was itself created using Silicon-on-Insulator (SOI) technology, such as the wafer bonding and layer transfer process described in the art.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was inappropriate because no trial date had been set in the parallel district court case, and the average time to trial in that district (D. Oregon) was 46.3 months.
  • Petitioner further argued against denial under General Plastic, asserting that this was its first IPR against the ’702 patent, it lacks a substantial relationship with another petitioner (Micron) who filed a separate IPR, this petition challenges different claims (including claim 1), and it was filed before the Patent Owner's Preliminary Response in the other IPR, thus avoiding any road-mapping concerns.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1 and 13-17 of Patent 7,378,702 as unpatentable.