PTAB

IPR2025-00485

NXP USA Inc v. Redstone Logics LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Power Management for a Multi-Core Processor
  • Brief Description: The ’339 patent discloses power management techniques for a multi-core processor. The technology involves applying dynamic voltage and frequency scaling (DVFS) to distinct sets of processor cores, allowing different groups of cores to operate at independent supply voltages and clock speeds to reduce power consumption while facilitating communication between them.

3. Grounds for Unpatentability

Ground 1: Obviousness over White and Talwar - Claims 1-3, 5, 8, 10-11, 14, and 21 are obvious over White in view of Talwar.

  • Prior Art Relied Upon: White (Patent 7,263,457) and Talwar (Application # 2009/0271646).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that White discloses a multi-core processor where each core can be configured to operate at frequencies and voltages independently of other cores. White further teaches an interface block (“common bridge logic”) for communication. Talwar discloses grouping processor cores into “clusters,” where each cluster receives power from a single voltage source and operates at a common frequency, which can be different from other clusters. Petitioner argued that applying Talwar’s clustering concept to White’s multi-core architecture directly maps to the claimed “first set” and “second set” of processor cores operating with independent supply voltages and clock signals. The combination also discloses an interface block for communication between these sets.
    • Motivation to Combine: A POSITA would combine these references to achieve the common goal of sub-chip-level DVFS in a processor with a large number of cores. White teaches per-core control, which becomes complex and costly as core count increases. Talwar’s clustering approach provides a known, practical, and efficient solution to manage DVFS for many cores, making it an obvious modification to scale White’s design.
    • Expectation of Success: The combination involved applying a known organizational strategy (clustering) to a known system (multi-core DVFS) to achieve predictable benefits in power management and design scalability.

Ground 2: Obviousness over Elgebaly and Ozer - Claims 1-3, 5, 8, 10-11, 14, and 21 are obvious over Elgebaly in view of Ozer.

  • Prior Art Relied Upon: Elgebaly (Application # 2007/0096775) and Ozer (Application # 2008/0209133).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Elgebaly teaches a multi-core system with adaptive voltage scaling where supply voltage and clock frequency can be set independently for each core or jointly for groups of cores. Elgebaly also discloses an internal shared memory but provides limited detail on its implementation. Ozer remedies this by disclosing a cache coherency method for shared memory in a multi-core processor, including a “cache coherency fabric” and snoop bus. Petitioner argued that Ozer’s cache coherency fabric and related circuitry constitute the claimed “interface block configured to facilitate communication” when implemented in Elgebaly’s system.
    • Motivation to Combine: A POSITA would combine Ozer with Elgebaly to improve memory access speed and power efficiency. Implementing a cache hierarchy and coherency mechanism, as taught by Ozer, was a standard and necessary design choice for any multi-core processor with shared memory to function efficiently. Ozer provided an obvious solution to implement the shared memory system mentioned but not detailed in Elgebaly.
    • Expectation of Success: Combining a standard cache coherency protocol with a multi-core processor was a routine and predictable step in processor design, ensuring that the resulting system would function as expected with improved performance.

Ground 3: Obviousness over White, Talwar, and Cho - Claims 5 and 14 are obvious over White and Talwar, further in view of Cho.

  • Prior Art Relied Upon: White (’457 patent), Talwar (’646 application), and Cho (Application # 2010/0073068).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground builds on the White/Talwar combination from Ground 1. Petitioner asserted that Cho discloses a temperature control unit (TCU) that monitors core temperatures and can reallocate processing loads between cores to manage thermal conditions. This TCU and its associated control signals meet the limitations of a “control block” that provides control signals to the processor cores, as required by dependent claims 5 (peripheral location) and 14 (central location), as Cho discloses both as obvious design choices.
    • Motivation to Combine: A POSITA would be motivated to add Cho’s functionality to the White/Talwar combination to introduce an additional, complementary method for thermal management. Combining workload reallocation (from Cho) with voltage/frequency scaling (from White/Talwar) would provide a more robust and flexible system for managing processor performance and temperature, a critical concern in multi-core design.
    • Expectation of Success: Adding a known thermal management technique to a multi-core processor was a predictable enhancement that would function as expected alongside existing DVFS power management systems.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations adding Vajda (Application # 2012/0060170) for thermal-aware processor layout guidance and Williams (a 2007 IEEE paper) for explicit teachings on using multiple crystal oscillators for independent clock generation.

4. Key Claim Construction Positions

  • Petitioner argued that the term “the first clock signal is independent from the second clock signal” requires the signals to be provided from, or processed from, different reference oscillator clocks.
  • This construction was based on arguments made by the Patent Owner during prosecution to overcome prior art that used a single reference clock.
  • Petitioner noted that the Patent Owner, in co-pending litigation, has asserted that "independent" simply means "different." Petitioner contended its arguments render the claims obvious under either construction.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial in view of a co-pending IPR (IPR2025-00085) filed by another party.
  • Petitioner asserted that denial under General Plastics or Advanced Bionics is inappropriate because Petitioners are not related to, are not co-defendants with, and are not accused of infringing with the same products as the petitioners in the other IPR.
  • Further, this petition relies on different prior art combinations and was timely filed shortly after Petitioner was sued, weighing against denial.

6. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-3, 5, 8-11, 14, and 21 of the ’339 patent as unpatentable.